GAA Nanosheet Transistors With Region-Specific Gate Oxide Thickness
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Solution Overview
Problem
The semiconductor industry faces challenges in continuously scaling down gate stacks for input/output (I/O) devices and core devices with varying gate oxide layer thicknesses to suit different high-voltage and high-speed applications.
Innovation Solution
The implementation of gate-all-around (GAA) devices with stacked nanosheet channels, where GAA devices in the core area have a thin gate oxide layer for high-speed applications and those in the I/O area have a thicker gate oxide layer for high-voltage applications, along with a method for forming these devices that includes specific gate oxide regrowth and high-k dielectric layer processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate oxide layer thickness is reduced for core devices to improve high-speed performance, then switching speed is improved, but device reliability deteriorates due to increased leakage and breakdown risks
Solution Approach 1:
The patent applies different gate oxide layer thicknesses to different device regions within the same integrated circuit. Core devices use thinner gate oxide layers (e.g., 5-15 nm) optimized for high-speed switching, while I/O devices use thicker gate oxide layers (e.g., 15-30 nm) optimized for reliability and voltage tolerance. This local differentiation allows each device type to operate at its optimal performance point without compromising the other.
Solution Approach 2:
The patent segments the integrated circuit into distinct functional regions (core region and I/O region) with independently optimized gate oxide thicknesses. This segmentation enables separate process control and performance optimization for each region, resolving the contradiction between speed and reliability by allowing thin-oxide core devices and thick-oxide I/O devices to coexist on the same chip.
2Reliability
If gate oxide layer thickness is increased for I/O devices to improve voltage tolerance, then device reliability is improved, but switching speed deteriorates
Solution Approach 1:
The patent implements local quality differentiation by assigning thicker gate oxide layers specifically to I/O devices that require high voltage tolerance and reliability, while keeping core devices with thinner gate oxide layers for high-speed operation. Each region's gate oxide thickness is locally optimized for its specific functional requirements.
Solution Approach 2:
The patent segments the circuit into I/O regions with thick gate oxide layers optimized for voltage tolerance and core regions with thin gate oxide layers optimized for speed, allowing each segment to perform its designated function at optimal performance levels.
3Adaptability or versatility
If different gate oxide layer thicknesses are used for core and I/O devices, then performance optimization for specific applications is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a uniform thick gate oxide layer across the entire substrate first, then using selective removal processes (such as targeted etching or sacrificial layer techniques) to thin the gate oxide only in the core device regions. This approach simplifies manufacturing by starting with a single deposition process and using selective removal rather than requiring multiple deposition processes with different thicknesses.
Solution Approach 2:
Instead of forming different thicknesses by depositing different amounts of oxide in different regions (the conventional approach), the patent inverts the process by first forming a uniform thick layer and then selectively removing material to create the desired thickness variation. This inversion simplifies the deposition process and allows for better process control.
4Reliability
If multiple gate structures are implemented to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent implements a universal gate structure design that serves multiple functions: it provides all-around gate control for improved device performance, enables different gate oxide thicknesses for different device types, and maintains compatibility with existing fabrication processes. The same basic gate structure is used throughout the circuit, with only the gate oxide thickness varying by region, rather than requiring fundamentally different gate structures for different device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible design integration schemes, enabling the optimization of circuits in different areas of the integrated circuit (IC) by choosing appropriate gate oxide thicknesses, thereby improving performance and reducing manufacturing costs.
Implementation Method 1
forming a first oxide layer over the first channel member and a second oxide layer over the second channel member
Implementation Method 2
performing an annealing process to increase a thickness of the second oxide layer under the capping layer
Data Source
AI summary
A semiconductor device includes a first transistor located in a first region of a substrate and a second transistor located in a second region of the substrate. The first transistor includes first channel members vertically stacked above the substrate and a first gate structure wrapping around each of the first channel members. The first gate structure includes a first interfacial layer. The second transistor includes second channel members vertically stacked above the substrate and a second gate structure wrapping around each of the second channel members. The second gate structure includes a second interfacial layer. The second interfacial layer has a first sub-layer and a second sub-layer over the first sub-layer. The first and second sub-layers include different material compositions. A total thickness of the first and second sub-layers is larger than a thickness of the first interfacial layer.