3D Gate-All-Around Vertical Gate Fabrication via Isotropic Etching
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Solution Overview
Problem
The fabrication of three-dimensional (3D) semiconductor devices faces challenges such as large footprints, reliability issues, and undesirable variations in performance, particularly in 3D vertical channel (VC) and vertical gate (VG) structures, due to difficulties in patterning, etching, and preventing deformation, defects, and bending.
Innovation Solution
A method for fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure involves forming alternating insulative material layers, identifying bit line and word line locations, removing portions of these layers to create vertical insulative material structures, and performing isotropic etching to support the remaining layers, thereby reducing deformation and defect occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If 3D vertical channel (VC) structures are fabricated, then storage capacity in smaller areas is achieved, but large footprint and reliability problems occur
Solution Approach 1:
The patent segments the vertical channel structure into multiple nanosheet channels stacked vertically, with each nanosheet providing separate conduction paths. This segmentation allows achieving high storage capacity in a small footprint while maintaining reliability through distributed stress and defect management across multiple independent channels
Solution Approach 2:
The patent implements a nested structure where gate electrodes wrap around each nanosheet channel in a gate-all-around configuration, with multiple gate layers nested around multiple nanosheet layers. This nested arrangement provides comprehensive control of each channel while maintaining a compact footprint, and enhances reliability through uniform stress distribution
2Area of stationary object
If 3D vertical gate (VG) structures are fabricated, then smaller footprint is achieved, but patterning and etching difficulties and deformation occur
Solution Approach 1:
The patent forms sacrificial mandrel structures and template layers before creating the final vertical gate structure. These preliminary structures guide the subsequent patterning and etching processes, enabling precise formation of the gate-all-around configuration while minimizing deformation through pre-established structural support
Solution Approach 2:
The patent introduces intermediate sacrificial materials and template layers that facilitate the complex patterning process. These intermediary structures enable precise definition of the vertical gate geometry during fabrication, and are subsequently removed to reveal the final structure, thereby achieving high manufacturing precision in difficult-to-fabricate features
3Quantity of substance
If 3D vertical channel (VC) structures are fabricated, then greater storage capacity is achieved, but undesirable variations in performance occur
Solution Approach 1:
The patent employs uniform materials and consistent fabrication processes across all nanosheet channels to ensure homogeneous electrical properties. The gate-all-around structure provides uniform control over each channel, and the stacked configuration ensures consistent stress and field distribution, thereby minimizing performance variations while maximizing storage capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reliable fabrication of 3D GAA VG structures with reduced footprints, minimizing deformation, defects, and stringer formation, leading to improved performance and reliability of semiconductor devices.
Implementation Method 1
performing an isotropic etching process to remove the second insulative material from the second insulative material layers
Implementation Method 2
The first and second insulative material layers may be formed by a deposition of first insulative material and second insulative material, respectively
Data Source
AI summary
Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.