GAAFET Drift Region Structure for Higher Operating Voltage

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Solution Overview

Problem

Existing semiconductor device structures, particularly GAAFET devices, face limitations in providing a diverse range of operating voltages, which restricts their application in high-power devices such as power amplifiers and RF amplifiers.

Innovation Solution

The semiconductor device structure includes a gate-all-around field-effect transistor (GAAFET) design with a depletion region and epitaxial layers that form a drift region, allowing for increased resistance to current flow at higher operating voltages, thereby expanding the operating voltage range to 1.8V-3.0V.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If conventional GAAFET device structures are used, then device simplicity is maintained, but the operating voltage range is limited

Engineering Contradiction:
Improveoperating voltage rangeVSAvoiddevice structure complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The device structure is segmented into distinct functional regions including a first drift region with first doping concentration and a second drift region with second doping concentration. This segmentation allows each region to contribute differently to the overall device performance, enabling extended operating voltage range while maintaining manageable structural complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the device are assigned different doping concentrations to optimize local electrical characteristics. The first drift region has a first doping concentration optimized for one aspect of voltage handling, while the second drift region has a second doping concentration optimized for another aspect, allowing the device to achieve diverse operating voltages through localized property variation

Inventive Principle:
Principle #3Local quality

2Power

If higher operating voltages are implemented, then high-power application capability is improved, but current flow resistance increases causing potential damage

Engineering Contradiction:
Improvehigh-power application capabilityVSAvoidcurrent flow resistance at high voltage
Core Design Contradiction:
PowerVSObject-affected harmful factors

Solution Approach 1:

The device utilizes parameter changes in doping concentration across different drift regions to manage current flow at high voltages. By varying the doping concentration from the first drift region to the second drift region, the device creates an optimized electrical profile that enables high-power operation while controlling harmful current flow effects through precise parameter modulation

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances the suitability of semiconductor devices for high-power applications by providing increased resistance to current flow at higher voltages, thus preventing damage and ensuring proper operation.

Implementation Method 1

a gate-all-around field-effect transistor (GAAFET) design with a depletion region and epitaxial layers that form a drift region

Methodology Applied
Scientific EffectDepletion region:

Implementation Method 2

allowing for increased resistance to current flow at higher operating voltages

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS20250126856A1Semiconductor device with increased operating voltage characteristics
Publication Date: 2025.04.17 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20250126856A1 patent drawing
  • US20250126856A1 patent drawing
  • US20250126856A1 patent drawing

AI summary

A semiconductor device, such as a gate-all-around field-effect transistor (GAAFET), that can provide advantages in terms of higher operating voltages. The semiconductor device includes a substrate with a p-type well, an n-type well, and a depletion region; an insulating layer disposed on the p-type well; a first epitaxial layer disposed on the insulating layer; a second epitaxial layer disposed on the p-type well, the n-type well, and/or the depletion region; and a gate formed around a channel and between the first epitaxial layer and the second epitaxial layer.