GAAFET Extended Source/Drain Structure for Lower REXT Delay

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Solution Overview

Problem

Gate-all-around field effect transistors (GAAFETs) face challenges with high parasitic resistance in the extended region under the spacer (REXT), leading to reduced on-state current and increased RC delay, particularly due to dopant diffusion during heat treatment processes like rapid thermal annealing.

Innovation Solution

The GAAFET design involves partially etching channels to reduce REXT resistance by shortening the channel length under the spacer without altering the gate structure, allowing for selective epitaxial growth of source/drain regions and subsequent laser annealing to prevent dopant diffusion, thereby increasing electrical conductivity and stress on the channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional heat treatment is used, then source/drain activation occurs, but extended region resistance increases due to low electrical conductivity under spacer

Engineering Contradiction:
Improvesource/drain activationVSAvoidextended region resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces conventional thermal field treatment with laser beam irradiation to activate dopants in the extended source/drain region. The laser provides precise energy delivery that activates dopants and improves electrical conductivity in the extended region without causing harmful thermal effects, thus reducing extended region resistance while maintaining source/drain activation.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Object-affected harmful factors

If channel length is reduced to reduce REXT, then extended region resistance decreases, but short-channel effect occurs

Engineering Contradiction:
Improveextended region resistanceVSAvoiddevice performance
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent applies different treatments to different regions: the channel length is maintained at conventional dimensions to avoid short-channel effect, while the extended source/drain region is selectively treated with laser annealing to improve electrical conductivity and reduce REXT. This localized differentiation allows reducing extended region resistance without causing short-channel effect.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances on-state current and reduces RC delay while avoiding the short-channel effect, enabling high-speed operation and improved performance by increasing the stress applied to the channels and maintaining the existing gate structure.

Implementation Method 1

Laser annealing is a process of irradiating a local region or a selected region with laser beams for a short period of time

Methodology Applied
Scientific EffectLaser annealing: Laser

Implementation Method 2

By laser annealing, non-diffusive activation of the dopants in the source/drain occurs

Methodology Applied
Scientific EffectNon-diffusive activation:

Implementation Method 3

dopants in the source/drain are diffused to a region having low electrical conductivity under the spacer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 4

allowing formation of a source/drain through epitaxial growth

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS20240282839A1Gate-all-around field-effect transistor with extended source/drain
Publication Date: 2024.08.22 POSTECH ACADEMY INDUSTRY FOUNDATION
  • US20240282839A1 patent drawing
  • US20240282839A1 patent drawing
  • US20240282839A1 patent drawing

AI summary

A gate-all-around field effect transistor with an extended source/drain and a method of manufacturing the same. The gate-all-around field effect transistor has an extended source/drain structure formed by partial etching of channels to solve unbalance between semiconductor devices and enables high speed operation through reduction in RC delay.