GAAFET and finFET Integration on Common Substrate
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Solution Overview
Problem
Current semiconductor production methods face challenges in simultaneously forming scalable core logic and I/O devices on a common substrate, as core logic requires downscaling and reduced voltages, while I/O devices need higher operating voltages, leading to size disparities and increased processing complexity.
Innovation Solution
A method for forming gate all around field effect transistors (GAAFETs) and fin field effect transistors (finFETs) on a common substrate using shared semiconductor features and processing steps, where GAAFETs are formed in one region and finFETs in another, with selective etching and masking techniques to create suspended semiconductor features and replace dummy gate stacks with metal gate stacks, allowing for efficient integration into existing CMOS production processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If core logic devices are downscaled to increase processing capability per unit area, then processing capability and energy efficiency are improved, but operating voltage is reduced which conflicts with I/O device requirements
Solution Approach 1:
The substrate is divided into distinct first and second regions, with the first region containing GAAFETs for core logic and the second region containing finFETs for I/O functionality. This spatial segmentation allows each region to be optimized independently for its specific functional requirements, enabling core logic to operate at lower voltages while I/O devices operate at higher voltages without mutual interference
Solution Approach 2:
Different transistor structures (GAAFET vs finFET) are implemented in different regions of the substrate according to local functional requirements. The GAAFETs in the first region provide scaled-down dimensions for high-density core logic, while the finFETs in the second region provide higher drive currents for I/O operations, allowing each local area to have the quality needed for its specific purpose
2Adaptability or versatility
If different types of components are combined on a single substrate, then device integration is improved, but processing complexity increases due to multiple different processing schemes
Solution Approach 1:
The method employs a universal set of processing steps that can form both GAAFETs and finFETs from similar starting semiconductor features. By using common processing techniques such as selective etching, dummy gate stack formation, and metal gate stack deposition, the process achieves multi-functionality, allowing a single processing flow to create different transistor types suitable for various device regions
Solution Approach 2:
Dummy gate stacks are introduced as intermediary structures during the fabrication process. These dummy gates serve as placeholders that enable subsequent processing steps (such as selective removal and metal gate formation) to be applied uniformly across different regions. The dummy gate stacks facilitate the formation of both GAAFET and finFET structures through the same processing sequence, thereby reducing overall process complexity
3Reliability
If I/O devices are made larger to handle higher operating voltages, then voltage handling capability is improved, but area utilization is reduced
Solution Approach 1:
By segregating I/O devices into a dedicated second region with finFET structures, the design allows these devices to occupy only the area necessary for their function without encroaching on core logic space. The finFET structure provides efficient area utilization while delivering the required voltage handling capability and drive current for I/O operations
Solution Approach 2:
The finFET structure in the second region is designed with optimized parameters (such as fin height, fin width, and channel length) to achieve the necessary voltage handling capability and drive current. By adjusting these geometric parameters, the I/O devices can handle higher operating voltages while maintaining compact dimensions that maximize area utilization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous formation of scalable core logic and I/O devices with minimal additional processing steps, leveraging the scalability of GAAFETs for digital circuitry and finFETs for high drive currents, thus addressing size and voltage disparities while simplifying production processes.
Implementation Method 1
the first semiconductor material layer is selectively removed along a longitudinal section of the first semiconductor feature by etching to form a suspended longitudinal first semiconductor feature of the remaining second semiconductor material layer
Implementation Method 2
the dummy gate stack is removed and replaced with a metal gate stack
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
According to an aspect of the present inventive concept there is provided a method for forming a gate all around field effect transistor (136), GAAFET, in a first region (104) of a substrate (101) and a fin field effect transistor (138), finFET, in a second region (106) of the substrate (101), the first region (104) including a first semiconductor feature (108) and the second region including a second semiconductor feature (110), each of said semiconductor features (108, 110) being a fin-shaped semiconductor feature (108, 110) including a vertical stack (150) of at least a first semiconductor material layer (152a, 152b) and a second semiconductor material layer (154a, 154b) arranged above the first semiconductor material layer (152a, 152b), the method comprising: selectively removing the first semiconductor material (152a, 152b) from a longitudinal section of the first semiconductor feature (108) by etching to form a suspended longitudinal first semiconductor feature (154a, 154b) of the remaining second semiconductor material (154a, 154b), while masking the second region (106) to counteract etching of the second semiconductor feature (110), and forming a gate all around electrode (132) on the suspended longitudinal first semiconductor feature (154a, 154b) in the first region (104) and a gate electrode (130) on the fin-shaped second semiconductor feature (110) in the second region (106).