GAAFET Nanowire Matrix Layout With BDI and Self-Aligned Gate Cut
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current gate-all-around field effect transistors (GAAFETs) face challenges in achieving optimal electrostatic control, large effective width for maximum drive current, bottom dielectric isolation for aggressively scaled effective gate lengths, and self-aligned gate cut for aggressive N-P boundary scaling.
Innovation Solution
The implementation of a semiconductor structure with a matrix of nanowires or nanosheets as the channel region, combined with bottom dielectric isolation and self-aligned gate cut, allows for the formation of GAAFETs with shared or isolated gate devices. This structure includes a vertical dielectric pillar separating pFET and nFET regions, enabling optimal electrostatic control and aggressive scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional GAAFET structures are used, then device density can be increased, but electrostatic control over the channel deteriorates
Solution Approach 1:
The gate electrode completely surrounds the nanowire channel in a nested configuration, with the gate wrapped around the channel region. This gate-all-around structure provides 360-degree electrostatic control of the channel, significantly improving voltage control and threshold voltage modulation compared to conventional planar or finFET structures while maintaining high device density.
Solution Approach 2:
The invention transitions from two-dimensional planar channels to three-dimensional vertically-oriented nanowire channels with surrounding gates. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sides), providing superior electrostatic control and enabling aggressive scaling of effective gate lengths while maintaining reliability.
2Productivity
If effective gate length is aggressively scaled, then device density increases, but achieving optimal electrostatic control becomes difficult
Solution Approach 1:
The gate electrode is nested around the nanowire channel in a gate-all-around configuration, providing electrostatic control from all directions. This nested structure maintains effective electrostatic control even as the effective gate length is aggressively scaled down, because the surrounding gate geometry provides better field control than planar structures at scaled dimensions.
Solution Approach 2:
The structure combines nanowire semiconductor material with surrounding gate materials and dielectric layers to form a composite gate-all-around structure. This composite approach enables precise control of electrical properties and electrostatic fields, supporting aggressive scaling of effective gate lengths while maintaining manufacturing precision and device performance.
3Reliability
If bottom dielectric isolation is implemented, then electrostatic control improves, but device complexity increases
Solution Approach 1:
A bottom dielectric layer is extracted and placed beneath the nanowire channel to provide electrical isolation and improve electrostatic control. This extracted dielectric component separates the channel from the substrate, reducing parasitic capacitance and enhancing gate control over the channel, while the overall fabrication process integrates this addition without proportionally increasing complexity.
Solution Approach 2:
The bottom dielectric layer serves multiple functions simultaneously: it provides electrical isolation between the channel and substrate, improves electrostatic control by reducing parasitic capacitance, and supports the vertical nanowire structure. This multi-functionality achieves improved electrostatic control without proportionally increasing device complexity.
4Productivity
If self-aligned gate cut is used, then N-P boundary scaling improves, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode is formed in advance to define the N-P boundary region, and subsequent processing steps are aligned to this pre-formed gate structure. This preliminary gate formation establishes a self-aligned reference that guides subsequent doping and patterning steps, enabling aggressive N-P boundary scaling while maintaining manufacturing precision through cumulative alignment to the gate rather than requiring multiple high-precision alignment steps.
Solution Approach 2:
The gate structure serves as its own alignment reference for subsequent processing steps. The self-aligned gate cut process uses the gate electrode geometry to automatically define the N-P boundary location, eliminating the need for separate alignment marks or complex multi-step alignment procedures. This self-service approach enables aggressive scaling while maintaining precision.
Data Source
AI summary
Provided is a semiconductor structure with shared gated devices. The semiconductor structure comprises a substrate and a bottom dielectric isolation (BDI) layer on top of the substrate. The structure further comprises a pFET region that includes a p-doped Source-Drain epitaxy material and a first nanowire matrix above the BDI layer. The structure further comprises an nFET region that includes a n-doped Source-Drain epitaxy material and a second nanowire matrix above the BDI layer. The structure further comprises a conductive gate material on top of a portion of the first nanowire matrix and the second nanowire matrix. The structure further comprises a vertical dielectric pillar separating the pFET region and the nFET region. The vertical dielectric pillar extends downward through the BDI layer into the substrate. The vertical dielectric pillar further extends upward through the conductive gate material to a dielectric located above the gate region.