GAAFET Source/Drain Isolation Structure for Leakage Suppression
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Solution Overview
Problem
Gate-all-around (GAA) nano-sheet and nano-wire FETs face challenges in maintaining uniform gate control and preventing leakage currents due to non-uniform shapes of bottommost SiGe layers during channel formation, leading to ineffective gate control and increased leakage currents.
Innovation Solution
Incorporation of isolation layers formed by flowable chemical vapor deposition (FCVD) over the side surfaces of the bottommost inner spacer structures to suppress leakage currents and improve gate capacitance, using silicon oxide to isolate source/drain epitaxial structures and enhance gate control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GAA nano-sheet and nano-wire FETs are used to achieve gate-all-around geometry, then gate control over channel regions is improved, but non-uniform shapes of bottommost SiGe layers cause leakage currents to increase
Solution Approach 1:
An isolation layer is introduced as an intermediary element between the bottommost inner spacer structure and the substrate. This isolation layer acts as a mediator that blocks leakage current paths while preserving the gate-all-around geometry's effective gate control. The isolation layer is deposited using flowable chemical vapor deposition (FCVD) to conformally cover the complex three-dimensional structure including the bottommost inner spacer and substrate interface.
Solution Approach 2:
The isolation layer is selectively positioned only at critical locations where leakage currents occur - specifically at the interface between the bottommost inner spacer structure and the substrate, and in regions adjacent to source/drain epitaxial structures. This localized approach addresses the leakage problem in specific areas without modifying the overall gate-all-around structure, maintaining high gate control while suppressing leakage locally.
2Reliability
If isolation layers are added to suppress leakage currents, then reliability is improved, but device complexity increases
Solution Approach 1:
The isolation layer is deposited early in the fabrication process, before source/drain epitaxial structures are formed. By performing this action preliminarily, the isolation layer is already in place to prevent leakage current formation, and subsequent processing steps can proceed without additional complexity. The FCVD process allows the isolation layer to conformally cover complex structures, eliminating the need for complex patterning steps that would otherwise be required.
Solution Approach 2:
The use of flowable chemical vapor deposition (FCVD) changes the deposition parameters and material flow characteristics to enable conformal coverage of three-dimensional structures. This parameter change allows the isolation layer to automatically adapt to complex geometries including sidewalls and recesses, reducing the need for additional processing steps and simplifying the overall device structure despite the added functional layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The isolation layers effectively block leakage current channels and improve gate capacitance, ensuring consistent gate control and reducing leakage currents in GAAFETs, thereby enhancing the performance of semiconductor devices.
Implementation Method 1
The isolation layers suppress a leakage current through the substrate between opposite source/drain epitaxial structures. The isolation layers also suppress a leakage current through the bottommost inner spacer structures between a gate structure of the GAAFETs and the source/drain epitaxial structures.
Implementation Method 2
Incorporation of isolation layers formed by flowable chemical vapor deposition (FCVD) over the side surfaces of the bottommost inner spacer structures
Implementation Method 3
the isolation layers effectively block leakage current channels and improve gate capacitance, ensuring consistent gate control
Data Source
AI summary
The present disclosure is directed to a structure of a gate-all-around field effect transistors (GAAFET) on a substrate and a method of forming the structure. The structure includes isolation layers below S/D epitaxial structures of the GAAFET. The isolation layers include silicon oxide and are formed by a flowable chemical vapor deposition process. The isolation layers are disposed over side surfaces of bottommost inner spacer structures of the GAAFET and protrude into the substrate. The isolation layers suppress a leakage current through the substrate between opposite S/D epitaxial structures. The isolation layers also suppress a leakage current through the bottommost inner spacer structures between a gate structure of the GAAFET and the S/D epitaxial structures.