GAAFET Sidewall Spacer Segmentation for Source/Drain Formation

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Solution Overview

Problem

Conventional gate-all-around field effect transistor (GAAFET) processing techniques are no longer suitable for continued device size scaling, as they fail to properly form epitaxial source/drain regions due to narrow source/drain openings with high aspect ratios, leading to isolation layer blockage during source/drain region formation.

Innovation Solution

The method involves forming a sacrificial gate on a multi-layer fin, performing sidewall spacer processing to create a gate section and fin sections, and selectively removing or reducing the fin sections without impacting the gate section, allowing for the widening of source/drain openings and selective removal of isolation material to ensure proper epitaxial source/drain region formation, enabling device size scaling while maintaining isolation element integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional GAAFET processing techniques are used, then device structure is formed, but source/drain openings become narrow with high aspect ratios preventing proper epitaxial source/drain region formation

Engineering Contradiction:

Improvesource/drain region formationVSAvoidsource/drain opening width

Core Design Contradiction:

Manufacturing precisionVSLength of moving object

Solution Approach 1:

The sidewall spacer is divided into two distinct sections: a gate section formed on the sacrificial gate and fin sections formed on exposed portions of the fin. This segmentation allows independent treatment of each section, enabling selective removal of fin sections while preserving the gate section for proper gate formation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The method performs preliminary actions by forming the sidewall spacer with distinct gate and fin sections before source/drain opening formation. The fin sections are then selectively removed to widen source/drain openings before epitaxial growth, ensuring proper source/drain region formation is enabled in advance.

Inventive Principle:

Principle #10Preliminary action

2Length of moving object

If fin sections of sidewall spacer are removed to widen source/drain openings, then source/drain region formation is enabled, but gate section integrity must be maintained

Engineering Contradiction:

Improvesource/drain opening widthVSAvoidgate section integrity

Core Design Contradiction:

Length of moving objectVSReliability

Solution Approach 1:

Different sections of the sidewall spacer are given different properties: the gate section maintains its full height and structural integrity to protect the gate, while the fin sections are selectively removed to widen source/drain openings. This local differentiation allows simultaneous achievement of widened openings and gate protection.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The gate section of the sidewall spacer acts as an intermediary protective structure during fin section removal. It shields the underlying gate from damage while allowing the fin sections to be removed for source/drain opening formation, mediating between the need for wide openings and gate protection.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If isolation material is deposited to form isolation elements, then electrical isolation is provided, but isolation material blocks source/drain region formation in narrow openings

Engineering Contradiction:

Improveelectrical isolationVSAvoidsource/drain region formation

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The method performs preliminary widening of source/drain openings by removing fin sections before isolation material deposition. This ensures sufficient space is created in advance for both isolation element formation and subsequent epitaxial source/drain region formation without blockage.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10431663B2Method of forming integrated circuit with gate-all-around field effect transistor and the resulting structure

Publication Date: 2019.10.01 GLOBALFOUNDRIES US INC

AI summary

Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.