GaN FET Probe Card RC Overlap Rapid RDS(ON) Testing

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Solution Overview

Problem

Conventional systems for testing gallium nitride (GaN) field effect transistors (FETs) are slow and inefficient, requiring lengthy high temperature operating life (HTOL) techniques to measure drain to source on resistance (RDS(ON)) and determine if the FET is operating within acceptable limits.

Innovation Solution

A probe card with a voltage terminal and current terminal coupled to a GaN FET through probe needles, including an overlap resistor-capacitor (RC) element and analog to digital (ADC) modules to rapidly switch the FET between cutoff and linear regions, measuring RDS(ON) within microseconds, and determining if it exceeds threshold levels or increases at an unacceptable rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional HTOL techniques are used to measure RDS(ON) of GaN FETs, then measurement reliability is improved, but testing time increases significantly

Engineering Contradiction:
Improvemeasurement reliabilityVSAvoidtesting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The probe card applies preliminary stress conditions (voltage and current) to the GaN FET before measurement to activate potential defects. The overlap RC element pre-charges capacitive nodes, and the test structure is configured in advance to detect early signs of device degradation, enabling rapid assessment without lengthy HTOL procedures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the measurement parameters by using specific voltage levels (e.g., 50V, 100V) and current conditions that stress the GaN FET to reveal defects quickly. The test method monitors RDS(ON) changes under controlled electrical parameters, allowing rapid detection of device issues that would otherwise require extended thermal aging.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If rapid switching between cutoff and linear regions is implemented, then testing speed is improved, but measurement complexity increases

Engineering Contradiction:
Improvetesting speedVSAvoidmeasurement complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The test method employs periodic switching of the GaN FET between cutoff and linear regions through controlled gate voltage application. This periodic stress pattern enables repeated measurements of RDS(ON) changes, allowing statistical analysis of device reliability while maintaining rapid test cycles that improve productivity.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If overlap RC element is used to inject current during transition, then measurement accuracy is improved, but circuit complexity increases

Engineering Contradiction:
Improvemeasurement accuracyVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The overlap RC element acts as an intermediary circuit component that facilitates accurate current injection during the FET transition period. The resistor-capacitor combination provides controlled charge transfer to the gate, enabling precise measurement of switching characteristics and RDS(ON) changes without requiring complex measurement instrumentation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240369614A1Probe card for device under test
Publication Date: 2024.11.07 TEXAS INSTRUMENTS INC
  • US20240369614A1 patent drawing
  • US20240369614A1 patent drawing
  • US20240369614A1 patent drawing

AI summary

A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.