GaN HEMT Channeled Ion Implantation for Normally-Off Operation
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Solution Overview
Problem
High-energy implantation in GaN HEMT transistor manufacturing introduces crystal defects, affecting dopant activation, threshold voltage, and electron mobility, leading to operational issues such as dynamic conduction resistance and reduced transistor performance.
Innovation Solution
Implementing a channeled ion implantation technique with precise orientation control, using magnesium, calcium, or fluorine ions at low energy to minimize crystal defects and achieve precise dopant distribution, thereby reducing the impact on the crystalline structure and enhancing the transistor's off-state breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If high-energy ion implantation is used to form the implanted zone in the GaN layer, then the implantation depth can reach satisfactory levels, but crystal defects are introduced that affect dopant activation and electron mobility
Solution Approach 1:
The patent changes the implantation energy parameter from high energy to low energy (less than 100 keV), and adjusts the implantation angle to be within 2 degrees of the crystal orientation. This parameter change allows achieving satisfactory implantation depth while minimizing crystal defects, thereby maintaining dopant activation efficiency and electron mobility.
2Manufacturing precision
If precise implantation inclination is used to control dopant profile, then the threshold voltage can be precisely controlled, but the manufacturing complexity increases
Solution Approach 1:
The patent simplifies the implantation process by changing the angle parameter to align with the crystal orientation (within 2 degrees), which naturally produces a desired dopant profile without requiring complex multi-angle or multi-step implantation sequences. This reduces manufacturing complexity while maintaining precise threshold voltage control.
3Length of stationary object
If high-energy implantation is used to overcome channeled implantation effects, then deeper implantation is achieved, but dynamic conduction resistance increases due to crystal defects
Solution Approach 1:
The patent changes the implantation energy to low energy (less than 100 keV) and aligns the implantation angle with the crystal orientation (within 2 degrees). This combination allows achieving adequate implantation depth while avoiding the generation of crystal defects that cause dynamic conduction resistance, thereby maintaining low on-state resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces crystal defects, improves dopant activation, and maintains high electron mobility, resulting in enhanced transistor performance and reliability, particularly in achieving a normally off-state operation with reduced conduction losses.
Implementation Method 1
an implantation step consisting in the implantation of magnesium, calcium or fluorine ions in the layer of GaN so as to form an implanted zone (8) in this layer of GaN
Implementation Method 2
Implementing a channeled ion implantation technique with precise orientation control, using magnesium, calcium, or fluorine ions at low energy to minimize crystal defects and achieve precise dopant distribution
Implementation Method 3
the electric field generated by the implanted zone makes it possible to create an insulating zone (depleted of carriers) at its vertical, at the interface between the GaN layer and the AlGaN layer
Data Source
Figure 1~4
Figure 5~6
Figure 7~8
AI summary
The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8).