Selectively Etched Surface Passivation for GaN HEMT Gate Leakage
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Solution Overview
Problem
GaN HEMT devices suffer from leakage current and trap-related phenomena such as current collapse and quiescent current drift due to defects in the AlGaN barrier layer, leading to gate leakage issues despite existing efforts like field plates and silicon nitride films.
Innovation Solution
The implementation of selectively etched surface passivation layers using multiple dielectric layers, where one dielectric layer acts as an etch stop to prevent damage during dry etching, and silicon nitride is used to passivate active areas, reducing gate leakage and ohmic contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching is used to define gate and ohmic contact areas, then manufacturing precision is improved, but surface damage occurs leading to increased gate leakage
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the surface passivation layer and the semiconductor substrate. This etch stop layer is selectively removed in gate and ohmic contact areas to allow dry etching, while protecting the surrounding surface passivation from etch damage. The etch stop layer acts as a mediator that enables precise gate definition without causing harmful surface damage to the passivation structure.
2Reliability
If surface passivation is applied across the entire active area, then reliability is improved by reducing surface traps, but gate leakage increases due to etch damage in gate areas
Solution Approach 1:
The surface passivation structure is designed with local quality variations through the selective removal of the etch stop layer. In gate areas, the etch stop layer is removed to allow controlled etching and reduce gate leakage, while in other active area regions, the etch stop layer remains to maintain surface passivation and reduce surface traps. This local differentiation resolves the contradiction between overall reliability improvement and localized gate leakage reduction.
3Object-generated harmful factors
If multiple dielectric layers are used for surface passivation, then gate leakage is reduced by preventing etch damage, but device complexity increases
Solution Approach 1:
The surface passivation is segmented into multiple functional dielectric layers: a surface passivation layer for trap reduction, an etch stop layer for selective removal and damage prevention, and optionally a buffer layer. This segmentation allows each layer to perform its specific function independently, reducing gate leakage through controlled etching while maintaining overall structural organization and manageability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate leakage and improves the consistency of ohmic contact resistances by avoiding etch damage and localizing surface passivation, thereby enhancing the performance of AlGaN/GaN HFET devices.
Implementation Method 1
A first dielectric layer is supported by the semiconductor substrate and extends across the active area. A second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate. The second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.
Implementation Method 2
silicon nitride is used to passivate active areas, reducing gate leakage and ohmic contact resistance
Implementation Method 3
This approach effectively reduces gate leakage and improves the consistency of ohmic contact resistances by avoiding etch damage and localizing surface passivation
Data Source
AI summary
A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.