GaN HEMT Gate Width Ratio for Linearity

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Solution Overview

Problem

High-frequency semiconductor devices like HEMTs face challenges in simultaneously suppressing inter-modulation distortion and leakage current, which are difficult to manage together for high output and linearity.

Innovation Solution

A semiconductor device design featuring a nitride semiconductor layer with an n-type gallium nitride layer, a channel layer, an electron supply layer, and specific electrode configurations, where the gate electrode's width to distance ratio (L/d1) is set to 7 or more, optimizing the band structure to reduce high-order conductance components and leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the gate electrode width to distance ratio (L/d1) is increased to suppress leakage current, then leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage current suppressionVSAvoidgate electrode configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by optimizing the gate electrode width to distance ratio (L/d1) to a specific value of 7 or more. This quantitative parameter adjustment simultaneously achieves leakage current suppression and maintains device simplicity, resolving the technical contradiction between reliability improvement and device complexity increase.

Inventive Principle:
Principle #35Parameter changes

2Object-generated harmful factors

If the band structure is optimized to reduce high-order conductance components, then inter-modulation distortion is reduced, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinter-modulation distortionVSAvoidlayer structure precision
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating a specific n-type gallium nitride layer with controlled doping concentration positioned between the channel layer and the ground layer. This localized structural modification with specific electrical properties reduces high-order conductance components and inter-modulation distortion while maintaining overall manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

3Object-generated harmful factors

If the n-type gallium nitride layer doping concentration is optimized to reduce tertiary inter-modulation distortion, then linearity is improved, but leakage current suppression becomes more difficult

Engineering Contradiction:
Improvetertiary inter-modulation distortionVSAvoidleakage current
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent introduces an n-type gallium nitride layer as an intermediary structure between the channel layer and the ground layer. This intermediate layer with specific doping concentration (1×10^18 to 1×10^19 atoms/cm³) acts as a mediator that simultaneously addresses both tertiary inter-modulation distortion reduction and leakage current suppression, resolving the contradiction between linearity improvement and reliability maintenance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9012958B2Semiconductor device
Publication Date: 2015.04.21 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US9012958B2 patent drawing
  • US9012958B2 patent drawing
  • US9012958B2 patent drawing

AI summary

A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with an underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1≧7, where L is the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; and d1 is the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.