GaN HEMT Isolation Chamber for Current Collapse Suppression

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Solution Overview

Problem

High voltage and high frequency semiconductor devices, such as Gallium nitride HEMT, experience a current collapse effect due to ionization of air and water vapor under strong electric fields, affecting performance and reliability.

Innovation Solution

A semiconductor device with an isolation structure that forms a sealed chamber over the gate, using a metallic material with a sealing structure taller than the isolation structure, minimizing dielectric layer thickness and parasitic capacitance, and employing a sub-isolation structure to optimize electric field distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a dielectric layer is disposed on the material surface to isolate air and water vapor, then the current collapse effect is suppressed, but the parasitic capacitance increases and high frequency performance deteriorates

Engineering Contradiction:
Improvecurrent collapse suppressionVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful dielectric layer from the device surface and replaces it with an air-filled isolation chamber. The chamber is formed by an isolation structure that encloses the gate region, with the interior space filled with air (or vacuum) instead of a solid dielectric material. This extraction eliminates the parasitic capacitance introduced by the dielectric layer while maintaining the isolation function against air and water vapor ionization.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates an inert environment within the isolation chamber by filling it with air (or vacuum) that is isolated from the external atmosphere. The isolation structure with sealing structures prevents external air and water vapor from entering the chamber, creating a controlled inert environment that suppresses ionization near the gate while not introducing parasitic capacitance like a dielectric layer would.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Reliability

If the isolation structure is made tall to improve sealing performance, then the isolation effect is enhanced, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvesealing performanceVSAvoidisolation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the isolation structure into multiple functional components: the isolation structure itself that defines the chamber, sealing structures that close the chamber openings, and support structures that provide mechanical stability. This segmentation allows each component to be optimized independently and simplifies the manufacturing process by enabling modular assembly.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces support structures as intermediary elements that connect the isolation structure to the substrate or other device components. These support structures serve as mediators that provide mechanical support and stability without interfering with the sealing function, thereby reducing the need for excessively tall isolation structures and simplifying the overall device architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the sealing structure height is increased to ensure proper sealing, then the sealing reliability is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvesealing reliabilityVSAvoidsealing structure precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs preliminary action by forming the isolation structure and chamber geometry before final sealing operations. The isolation structure is constructed with pre-defined sealing surfaces and geometries that guide the subsequent sealing process, ensuring proper alignment and contact between sealing components. This preliminary structuring reduces the precision requirements during final sealing by providing built-in alignment features.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes thin film sealing structures that conform to the isolation chamber geometry. These flexible thin films can adapt to minor variations in the isolation structure dimensions and surface roughness, providing reliable sealing without requiring extremely tight manufacturing tolerances. The thin film nature also minimizes the added height and complexity compared to rigid sealing structures.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively isolates air and water vapor, preventing current collapse and improving high frequency performance while maintaining manufacturing simplicity and reliability.

Implementation Method 1

disposing a sealing structure to seal an opening of the chamber in the gate extending direction to form a sealed chamber

Methodology Applied
Scientific EffectPhysical Containment: Physical Containment

Implementation Method 2

the electric field between the source and drain regions (especially in the region of the gate close to the drain) is very strong. Such a strong electric field may cause ionization of air and air vapor above the material surface, generate ions

Methodology Applied
Scientific EffectIonization: Ionisation

Data Source

PatentUS10749005B1Semiconductor device and method for manufacturing the same
Publication Date: 2020.08.18 DYNAX SEMICON
  • US10749005B1 patent drawing
  • US10749005B1 patent drawing
  • US10749005B1 patent drawing

AI summary

The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device according to a performing mode includes a substrate, a semiconductor layer located on one side of the substrate, a source and a drain located on one side of the semiconductor layer away from the substrate, and a gate located between the source and the drain, and an isolation structure disposed on one side of the semiconductor layer away from the substrate, one end of the isolation structure being disposed at a side close to the source, and the other end being disposed at a side close to the drain and in direct contact with the surface layer of the semiconductor device, the isolation structure covering the gate or a part of the gate, the isolation structure being an integrally formed structure and forming a chamber with the semiconductor layer.