GaN HEMT Enhancement Mode Gate via Passivation Etching
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Solution Overview
Problem
Existing enhancement mode transistors face challenges in achieving a normally-off operation with low on-state resistance and minimal surface state creation, due to non-selective dry etching techniques that introduce defects and dispersion effects, making it difficult to reproducibly etch AlGaN layers and form a recessed gate without additional processing steps.
Innovation Solution
A method involving the deposition of a passivation layer on a GaN/AlGaN heterostructure, where holes are etched in the passivation layer without protruding into the underlying layers, allowing a gate contact to be placed without creating a 2DEG underneath, enabling a normally-off operation by applying a positive voltage above a threshold voltage to induce a 2DEG between the active layers for current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-selective dry etching techniques are used to etch AlGaN layers, then enhancement mode operation can be achieved, but surface states are created and dispersion effects occur
Solution Approach 1:
A passivation layer is introduced as an intermediary between the gate contact and the AlGaN layer. This passivation layer prevents direct interaction between the gate etching process and the AlGaN surface, thereby avoiding the creation of surface states and dispersion effects while still enabling enhancement mode operation through controlled etching of the passivation layer only.
2Reliability
If recessed gate is formed by etching AlGaN layer, then normally-off operation is achieved, but additional processing steps are required
Solution Approach 1:
The device structure is segmented into distinct functional layers: a passivation layer separate from the AlGaN active layer. This segmentation allows the gate contact to be formed by etching only the passivation layer, achieving normally-off operation without requiring etching of the AlGaN layer itself, thereby reducing processing complexity.
3Reliability
If passivation layer is deposited on AlGaN surface, then surface states are stabilized, but on-state resistance increases
Solution Approach 1:
The passivation layer is applied selectively and locally only in the gate region, not across the entire device surface. This localized passivation stabilizes surface states at the gate contact area without interfering with the 2DEG formation and transport in the channel region, thereby maintaining low on-state resistance while achieving surface state stabilization where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the controllability of the fabrication process, achieves low on-state resistance, minimizes surface state creation, and preserves passivation, resulting in a high channel current density and reduced Ohmic contact resistances, while maintaining the 2DEG density in other regions.
Implementation Method 1
the passivation is able to stabilize the surface states of the AlGaN surface. This reduces the DC-to-RF dispersion
Implementation Method 2
This 2DEG layer is a consequence of piezoelectric polarization leading to charge separation within the materials
Implementation Method 3
A certain negative voltage, called threshold voltage, on the gate is needed to deplete the 2DEG through capacitive coupling
Data Source
AI summary
A method is disclosed for producing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET or MESFET devices, comprising two active layers, e.g. a GaN/AlGaN layer. The method produces an enhancement mode device of this type, i.e. a normally-off device, by providing a passivation layer on the AlGaN layer, etching a hole in the passivation layer and not in the layers underlying the passivation layer, and depositing the gate contact in the hole, while the source and drain are deposited directly on the passivation layer. The characteristics of the active layers and/or of the gate are chosen such that no two-dimensional electron gas layer is present underneath the gate, when a zero voltage is applied to the gate. A device with this behavior is also disclosed.