Selectively Etched Surface Passivation for GaN HEMT Gate Leakage
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Solution Overview
Problem
GaN HEMT devices suffer from leakage current and trap-related phenomena such as current collapse and quiescent current drift due to defects in the AlGaN barrier layer, leading to gate leakage issues despite efforts like field plate reduction and silicon nitride film use.
Innovation Solution
The implementation of selectively etched surface passivation layers using multiple dielectric layers, where one dielectric layer acts as an etch stop to avoid damage during dry etching, and silicon nitride is used to prevent current collapse by doping the GaN layers and protecting the gate and ohmic contact areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching is used to define gate and ohmic contact areas, then manufacturing precision is improved, but surface damage occurs leading to increased gate leakage
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the surface passivation layer and the GaN substrate. This etch stop layer absorbs the damage from dry etching processes, preventing direct damage to the GaN surface while still allowing precise definition of gate and ohmic contact areas through selective etching.
Solution Approach 2:
The surface passivation structure is segmented into multiple layers: an outer surface passivation layer for protection, an intermediate etch stop layer for damage absorption, and the GaN substrate. This segmentation allows each layer to perform its specific function independently, with the etch stop layer specifically designed to protect against etch damage.
2Reliability
If surface passivation is applied to protect GaN surface, then reliability is improved, but etch damage occurs during subsequent processing
Solution Approach 1:
The etch stop layer serves as a mediator between the surface passivation layer and the etching process. It allows the surface passivation layer to provide protection while the etch stop layer absorbs the harmful effects of etching, enabling both functions to coexist without interference.
Solution Approach 2:
The etch stop layer is deposited beforehand to provide a cushioning effect against subsequent etching processes. This pre-positioned layer anticipates and prevents etch damage to critical surfaces, allowing aggressive etching conditions to be used without compromising surface integrity.
3Ease of manufacture
If aluminum oxide is used as surface passivation, then ease of manufacture is improved, but inconsistent ohmic contact resistance occurs
Solution Approach 1:
The etch stop layer acts as an intermediary that decouples the surface passivation function from the ohmic contact formation process. By providing a dedicated etch stop function, it allows aluminum oxide to be used for passivation without directly interfering with ohmic contact resistance uniformity, as the etch stop layer absorbs processing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate leakage and ensures consistent ohmic contact resistances by minimizing etch damage and optimizing surface passivation, thereby enhancing the performance and reliability of AlGaN/GaN HFET devices.
Implementation Method 1
depositing an etch stop dielectric layer on the surface in the active area... The etch stop dielectric layer prevents damage to the GaN surface during dry etching of the passivation layer
Implementation Method 2
silicon nitride is used to prevent current collapse by doping the GaN layers
Data Source
AI summary
A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.