GaN Polarization Super Junction for Voltage-Speed Tradeoff
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Solution Overview
Problem
Semiconductor devices using gallium nitride (GaN) face challenges with current collapse due to high electric fields, which existing technologies like field plates and super junction structures cannot fully address, especially at high voltage applications, and polarization super junction devices struggle to optimize voltage resistance and dynamic characteristics simultaneously.
Innovation Solution
A semiconductor device with a polarization super junction region and a separate p-electrode contact region, featuring specific layer thicknesses and doping concentrations, is designed to enhance two-dimensional hole and electron gas formation, allowing for improved voltage resistance and high-speed operation by optimizing the p-type GaN layer and p-electrode contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If field plate technology is applied to control peak electric field, then voltage resistance is improved, but device complexity increases and current collapse is not sufficiently controlled
Solution Approach 1:
The device is divided into distinct functional regions: a polarization super junction region for voltage resistance and a separate p-electrode contact region for electrical contact. This segmentation allows each region to be optimized independently, reducing overall device complexity while maintaining high voltage resistance through the specialized polarization super junction structure with alternating p-type and n-type semiconductor layers.
Solution Approach 2:
A polarization layer is introduced as an intermediary between the p-type and n-type semiconductor layers. This polarization layer generates bound charges that compensate for ionized impurity charges, thereby controlling the electric field distribution and reducing peak electric field intensity without requiring complex field plate structures.
2Strength
If polarization super junction structure is used, then voltage resistance is enhanced, but dynamic characteristics deteriorate due to tradeoff between voltage resistance and high-speed operation
Solution Approach 1:
Different regions of the semiconductor structure are assigned different doping concentrations and layer thicknesses to optimize local properties. The polarization super junction region has optimized layer parameters for voltage resistance, while the separate p-electrode contact region provides low-resistance electrical contact for high-speed operation, allowing each region to perform its function optimally without compromising the other.
Solution Approach 2:
The invention optimizes specific parameters including the thickness of each semiconductor layer, the doping concentration of ionized impurities, and the composition ratio in the polarization layer. By carefully adjusting these parameters, the device achieves both high voltage resistance through enhanced polarization effects and fast dynamic characteristics through reduced charge transport distances and optimized electrical contact.
3Power
If high voltage is applied between gate and drain, then switching capability is improved, but current collapse occurs due to electron trapping in surface states
Solution Approach 1:
The invention converts the harmful effect of ionized impurity charges, which normally cause peak electric field and current collapse, into a beneficial effect. By introducing a polarization layer that generates bound charges with opposite polarity, these bound charges compensate for the ionized impurity charges, transforming the harmful space charge region into a controlled electric field distribution that prevents electron trapping while maintaining switching capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively overcomes the tradeoff between high voltage resistance and high-speed operation, reducing current collapse and achieving low loss, while maintaining excellent heat dissipation through a flip-chip mounted structure.
Implementation Method 1
a polarization super junction region... a two-dimensional hole gas being formed in the second undoped GaN layer in the vicinity part of a hetero-interface between the undoped AlxGa1-xN layer and the second undoped GaN layer, and a two-dimensional electron gas being formed in the first undoped GaN layer in the vicinity part of a hetero-interface between the first undoped GaN layer and the undoped AlxGa1-xN layer
Data Source
AI summary
Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25 nm and not larger than 47 nm and 0.17≤x≤0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10−18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w [cm−3] of the p-type GaN layer 14, tR≥0.864/(x−0.134)+46.0 [nm] is satisfied. The p-electrode contact region comprises a p-type GaN contact layer formed to be in contact with the p-type GaN layer 14 and a p-electrode that is in contact with the p-type GaN contact layer.