Enhancement Mode GaN Transistor via Selective Thermal Oxidation
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Solution Overview
Problem
Existing semiconductor devices with 2-DEG layers are typically normally-on devices, requiring a negative gate voltage to deplete the electron channel, which is not suitable for applications like power switching and digital electronics. Achieving a normally-off device configuration with high 2-DEG density and improved performance is challenging due to poor control over the semiconductor-oxide interface and detrimental effects from gallium oxidation.
Innovation Solution
A method for forming an enhancement mode transistor with a Ga-free second active layer, comprising InxAl1-xN, where x is between 0 and 0.5, using thermal oxidation to create a gate insulating layer that locally depletes the 2-DEG under the gate electrode, ensuring the 2-DEG layer is only present outside the gate region, and using high dielectric constant materials for improved reliability and reduced gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 2-DEG layer is present in the heterostructure to enable current conduction, then the device can conduct current between source and drain, but the device becomes normally-on requiring negative gate voltage to deplete the channel
Solution Approach 1:
The patent applies local quality by creating different regions with different 2-DEG densities. The gate contact region has depleted 2-DEG (low electron density) while the source/drain regions maintain high 2-DEG density. This is achieved through selective processing that removes or depletes the 2-DEG only under the gate contact, allowing the device to be normally-off while preserving current conduction capability in the source/drain regions.
2Reliability
If gate recess technology is used to decrease gate to channel distance, then positive threshold voltage is achieved, but device performance deteriorates
Solution Approach 1:
The patent changes the parameter of 2-DEG density distribution rather than physically recessing the gate. By controlling the 2-DEG formation parameters through material composition (InxAl1-xN barrier layer) and processing conditions, the patent achieves positive threshold voltage while maintaining optimal gate-to-channel distance and preserving high current density capability.
3Reliability
If fluorine implantation is used to locally deplete 2-DEG, then normally-off operation is achieved, but device performance is poor
Solution Approach 1:
Instead of using fluorine implantation to deplete 2-DEG, the patent extracts the harmful implantation process entirely. The depletion is achieved through selective thermal processing that thermally activates the heterostructure to form 2-DEG only in desired regions, eliminating the need for damaging ion implantation while achieving the same normally-off operation.
4Reliability
If deposited oxide gate dielectric is used in MISHEMT, then normally-off operation is possible, but interface control is difficult preventing full potential utilization
Solution Approach 1:
The patent employs self-service by using in-situ grown oxide gate dielectric that forms directly on the semiconductor surface during the growth process. This self-formed interface eliminates the need for separate deposition processes and ensures optimal interface quality and control, allowing the MISHEMT to achieve its full potential with excellent interface characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in a significantly enhanced thermal stability and reduced gate leakage current, enabling a larger temperature domain for processing and improved device reliability by avoiding interfacial states and gallium oxide formation, thus achieving a normally-off device with high current density and reliability.
Implementation Method 1
oxidizing at least a part of the second active layer by thermal oxidation thereby forming a gate insulating layer
Implementation Method 2
This 2-DEG layer is a result of piezoelectric and spontaneous polarization leading to charge separation within the materials
Implementation Method 3
This 2-DEG layer is a result of piezoelectric and spontaneous polarization leading to charge separation within the materials
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present invention provides a semiconductor device (10) comprising a first active layer (3) on a substrate (1), a second active layer (4) on the first active layer (3), the second active layer (4) having a higher bandgap compared to the first active layer (3), being substantially Ga-free and comprising at least Al, a gate insulating layer (5) on at least a part of the second active layer (4), the gate insulating layer (5) being formed by thermal oxidation of at least a part of the second active layer (4), a gate electrode (6) on at least a part of the gate insulating layer (5) and a source electrode (7) and drain electrode (8) on the second active layer (4). The semiconductor device (10) furthermore comprises, when in operation and when the gate electrode (6) and source electrode (7) are at a same voltage, a two-dimensional electron gas (2-DEG) layer between the first active layer (3) and the second active layer (4) only outside the location of the gate electrode (6) and not at the location of the gate electrode (6). The present invention also provides a method for forming such a semiconductor device (10).