Gate-All-Around Nanowire FET With Variable Thickness Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistor dimensions are scaled down to sub 20-25 nm technology nodes, further improvements are required in gate-all-around (GAA) FETs to enhance control over the channel region, particularly addressing the incomplete control of the bottom side of the channel in FinFETs and the short-channel effects in GAA FETs.
Innovation Solution
A method for fabricating a GAA FET involves forming stacked semiconductor layers with varying thicknesses to create fin structures, embedding them in an isolation insulating layer, and wrapping gate electrodes around these structures to ensure comprehensive control over the channel region, including the bottom side, through a series of epitaxial growth, patterning, and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FinFET gate structure is used to control channel current, then three side surfaces of channel are controlled, but the bottom part of channel is far away from gate electrode and not under close gate control
Solution Approach 1:
The patent transitions from planar FinFET gate structure to three-dimensional gate-all-around structure, where the gate electrode completely surrounds the nanowire channel in all spatial dimensions. This dimensional change enables the gate to control the channel from top, bottom, and sides simultaneously, eliminating the unreachable bottom region in FinFETs.
Solution Approach 2:
The gate electrode is positioned inside and completely surrounding the nanowire channel, creating a nested configuration where the gate is embedded within the channel structure. This nested arrangement ensures maximum gate control over the entire channel perimeter including the bottom surface.
2Reliability
If GAA FET structure is used to surround all side surfaces of channel, then fuller depletion is achieved, but short-channel effects still occur due to scaling challenges
Solution Approach 1:
The patent employs selective epitaxial growth to form nanowire structures with precisely controlled thicknesses before gate formation. By pre-establishing uniform nanowire dimensions and spacing through controlled deposition processes, the subsequent gate-all-around structure can achieve complete depletion without manufacturing variability compromising performance.
Solution Approach 2:
The patent utilizes controlled epitaxial growth parameters including temperature, pressure, and precursor ratios to precisely regulate nanowire thickness and spacing. By adjusting these process parameters, uniform nanowire structures are formed that enable effective gate control while minimizing short-channel effects at scaled dimensions.
3Productivity
If transistor dimensions are scaled down to sub 20-25 nm, then device density and performance are improved, but control over channel region becomes more difficult
Solution Approach 1:
The patent employs vertical nanowire structures with gate-all-around configuration, transitioning from two-dimensional planar control to three-dimensional volumetric control. This dimensional approach maintains effective gate control over the channel even as horizontal dimensions are scaled down to sub-20nm nodes, enabling continued device density improvement without sacrificing channel control reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the control over the channel region, reducing short-channel effects and enhancing the driving current of the GAA FETs by ensuring uniform thickness and spacing of nanowires, thereby improving device performance.
Implementation Method 1
a gate electrode is adjacent to three side surfaces of a channel region with a gate dielectric layer interposed therebetween... the gate structure surrounds (wraps) the fin on three surfaces, the transistor essentially has three gates controlling the current through the fin or channel region
Implementation Method 2
forming stacked semiconductor layers with varying thicknesses to create fin structures... through a series of epitaxial growth, patterning, and etching processes
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction. Each of the first semiconductor layers at the first portion of the first semiconductor layers have a substantially same thickness.