GaAs Diode Defect Layer Leakage Reduction
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Solution Overview
Problem
High-voltage semiconductor diodes face challenges in achieving low on-state resistances and low leakage currents, especially at high voltages and elevated temperatures, while maintaining high dielectric strength and being cost-effective.
Innovation Solution
A stacked III-V semiconductor diode structure incorporating a defect layer produced by liquid phase epitaxy or MOVPE, with the defect layer spaced from the space charge zone to reduce leakage currents and enhance manufacturing robustness, allowing for lower on-resistances and capacitances, and enabling operation across a wide voltage range with high thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional high-voltage semiconductor diode structure is used, then high dielectric strength is achieved, but leakage currents increase significantly at high voltages and elevated temperatures
Solution Approach 1:
An intermediate defect layer is introduced between the heavily doped contact region and the intrinsic layer. This defect layer acts as a mediator that captures and recombines minority carriers, preventing them from reaching the depletion region and causing leakage currents. The layer is positioned outside the space charge zone to avoid interfering with the high-voltage blocking capability while effectively reducing leakage.
Solution Approach 2:
The defect layer is localized to a specific region (the intermediate layer between the heavily doped contact and the intrinsic layer) rather than being distributed throughout the entire device. This localized approach allows the rest of the device to maintain its high-voltage blocking properties while only the specific region introduces carrier recombination to reduce leakage.
2Reliability
If the defect layer is positioned close to the space charge zone, then leakage current reduction is maximized, but manufacturing precision requirements increase
Solution Approach 1:
The defect layer is formed during the epitaxial growth process itself, before subsequent device fabrication steps. By incorporating the defect layer into the epitaxial structure from the beginning, the positioning is determined by the epitaxial growth parameters rather than requiring precise post-growth alignment, thereby reducing manufacturing precision requirements.
3Ease of manufacture
If III-V semiconductor materials are used instead of Si or SiC, then cost-effectiveness and thermal stability are improved, but achieving low on-resistances at high voltages becomes more challenging
Solution Approach 1:
The device uses a composite structure combining heavily doped contact regions (providing low resistance) with an intrinsic layer and defect layer (providing high-voltage blocking). The heavily doped contact regions are optimized for low series resistance while the intrinsic-defect layer combination provides the high-voltage blocking capability, achieving both low on-resistance and high voltage withstand in a III-V material system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The diode achieves significantly reduced leakage currents by more than an order of magnitude, supports high switching frequencies and current densities, and is more cost-effective than Si or SiC diodes, with improved thermal stability up to 300°C, making it suitable for high-voltage applications.
Implementation Method 1
the defect layer can be produced in different ways, for example by implantation or by incorporating foreign atoms, and that charge carriers recombine within the defect layer
Implementation Method 2
a stacked III-V semiconductor diode (10) consisting of a heavily doped contact region (n + -region, p + -region), an intrinsic layer, a lightly doped region (n -region, p -region) and a defect layer
Data Source
Figure 1~3
Figure 4~5
AI summary
Stacked III-V semiconductor diode (10) comprising an n+ layer (12) with a dopant concentration of at least 1019 N/cm3, an n- layer (14) with a dopant concentration of 1012-1016 N/cm3, a layer thickness (D2) of 10-300 µm, a p+ layer (18) with a dopant concentration of 5•1018-5•1020 cm3, with a layer thickness (D3) greater than 2 µm, wherein the layers follow one another in the aforementioned order, and each comprising a GaAs compound, the n+ layer (12) or the p+ layer (18) being formed as a substrate, and a bottom surface of the n- layer (14) being metallurgically bonded to a top surface of the n+ layer (12), and between the n- layer (14) and the p+ layer (18) a doped intermediate layer (15) is arranged,and with a top and a bottom, and the bottom of the intermediate layer (15) is metallurgically bonded to the top of the n--layer (14) and the top of the intermediate layer is metallurgically bonded to the bottom of the p+-layer (18), and wherein the intermediate layer (16) is metallurgically bonded to the n--layer (14) and to the p+-layer (18) and is p-doped, and the stacked III-V semiconductor diode (10) comprises a first defect layer (16) with a layer thickness (D4) greater than 0.5 µm, the defect layer (16) is arranged within the p'-layer, and the defect layer (16) has a defect concentration in the range between 1 × 10¹³ N/cm³ and 5 × 10¹⁶ N/cm³.