Gate-All-Around IC Structure with Remnant Liner Stubs
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Solution Overview
Problem
Modern integrated circuits face challenges such as fin bending, collapsing, and non-uniformity due to the miniaturization of finFETs and gate-all-around structures, which affect the control of channel regions and increase fabrication complexity and costs.
Innovation Solution
The proposed solution involves forming a gate-all-around integrated circuit structure with insulator regions and remnant liner stubs that support the fins, ensuring uniformity and stability during fabrication by using a method that includes forming pillars, recessing insulators, and conformally depositing liners along the fin sidewalls to prevent bending and collapsing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If finFETs and gate-all-around structures are miniaturized to increase device density, then the number of transistors per chip area increases, but fin bending and collapsing occur due to reduced structural support
Solution Approach 1:
A liner is formed on the fin sidewalls before the gate-all-around structure is completely fabricated. This preliminary formation of the liner provides structural support to the fins during subsequent fabrication steps, preventing bending and collapsing that would otherwise occur due to miniaturization. The liner acts as a preventive measure established in advance to maintain fin integrity throughout the fabrication process.
Solution Approach 2:
The liner serves as an intermediary structural element between the fin and the gate-all-around structure. It provides mechanical support to the miniaturized fins while allowing the gate structure to wrap around the channel, thus mediating between the need for high device density and the need for fin structural stability during fabrication.
2Ease of manufacture
If traditional planar FET fabrication methods are used, then manufacturing processes are simpler, but electrostatic control and electron mobility deteriorate at scaled dimensions
Solution Approach 1:
The patent transitions from traditional planar FET fabrication to a gate-all-around three-dimensional structure. The gate wraps around the channel in multiple dimensions, providing superior electrostatic control and electron mobility at scaled dimensions while maintaining compatibility with modified fabrication processes that include liner formation for structural support.
3Productivity
If very small fin pitch is used to increase device density in 7nm and beyond, then more transistors fit on chip, but fin bending and material etch non-uniformity increase
Solution Approach 1:
The liner is formed on fin sidewalls before subsequent etching and fabrication steps. This preliminary protective layer ensures uniform material etching and maintains fin straightness even at very small pitches below 20nm, preventing the non-uniformity that would otherwise occur due to etch loading effects and reduced spacing between adjacent fins.
4Device complexity
If gate-all-around structures are formed without liner support, then fabrication steps are reduced, but fin bending and collapsing occur during manufacturing
Solution Approach 1:
The liner acts as a temporary intermediary structure that provides mechanical support during fabrication. It is formed early in the process and removed after serving its protective function, enabling the fabrication of gate-all-around structures without fin collapsing while adding minimal complexity to the overall process.
Solution Approach 2:
The liner is formed as a temporary structure that is discarded after serving its protective function during fabrication. This temporary addition enables the successful creation of gate-all-around structures, and the liner is subsequently removed to leave the final device structure without permanent additional components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents fin bending and collapsing, ensures uniform fin reveal, and simplifies the fabrication process, leading to more reliable and cost-effective integrated circuit structures with improved performance.
Implementation Method 1
conformally depositing liners along the fin sidewalls
Data Source
AI summary
The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.