GaAs Substrate Crack Reduction via Local Dislocation Control
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Solution Overview
Problem
Gallium arsenide crystal substrates with flat and notch portions suffer from high crack defect ratios during manufacturing and epitaxial layer growth due to defects in the flat and notch regions, which are not adequately addressed by existing methods that focus on average dislocation density and residual strain across the entire wafer rather than specific regions.
Innovation Solution
A gallium arsenide crystal substrate with a diameter of 150 mm to 205 mm and thickness of 300 μm to 800 μm, containing silicon and carbon atoms within specific concentration ranges, is designed to have controlled average dislocation density and residual strain in flat and notch regions, reducing crack defects by adjusting these parameters in the substrate's manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If flat portion and notch portion are formed in the outer edge of the gallium arsenide crystal substrate, then the substrate can be used for semiconductor devices, but crack defects occur in the flat and notch regions during manufacturing and epitaxial layer growth
Solution Approach 1:
The patent applies local quality by specifying different dislocation density requirements for different regions of the substrate. The flat region and notch region are given special attention with dislocation density of 1×10^4 cm^-2 or less, while other regions can have higher dislocation density up to 5×10^4 cm^-2. This regional differentiation allows the substrate to be usable for semiconductor devices while minimizing crack defects in critical areas.
2Manufacturing precision
If average dislocation density is reduced across the entire wafer, then overall crystal quality improves, but the specific defect issues in flat and notch regions are not adequately addressed
Solution Approach 1:
The patent implements local quality control by establishing region-specific dislocation density criteria. The flat region and notch region require dislocation density of 1×10^4 cm^-2 or less, while other regions can tolerate up to 5×10^4 cm^-2. This approach addresses the specific defect issues in flat and notch regions without requiring excessive reduction of average dislocation density across the entire wafer, thus resolving the contradiction between manufacturing precision and reliability.
3Reliability
If silicon and carbon atoms are added to the gallium arsenide crystal substrate, then electrical properties are improved, but dislocation density may increase
Solution Approach 1:
The patent applies parameter changes by precisely controlling the concentration ranges of silicon (3.0×10^16 to 3.0×10^19 cm^-3) and carbon (1.0×10^15 to 5.0×10^17 cm^-3) atoms. These parameter specifications optimize electrical properties while maintaining dislocation density within acceptable limits (1×10^4 cm^-2 or less in flat and notch regions), thus resolving the contradiction between reliability and manufacturing precision.
Data Source
AI summary
A gallium arsenide crystal substrate has a diameter not smaller than 150 mm and not greater than 205 mm and a thickness not smaller than 300 μm and not greater than 800 μm and includes any of a flat portion and a notch portion. In any of a first flat region and a first notch region, when an atomic concentration of silicon is not lower than 3.0×1016 cm−3 and not higher than 3.0×1019 cm−3, the gallium arsenide crystal substrate has an average dislocation density not lower than 0 cm−2 and not higher than 15000 cm−2, and when an atomic concentration of carbon is not lower than 1.0×1015 cm−3 and not higher than 5.0×1017 cm−3, the gallium arsenide crystal substrate has an average dislocation density not lower than 3000 cm−2 and not higher than 20000 cm−2.