GAA FET Source/Drain Epitaxial Layers for Gate Control

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Solution Overview

Problem

As semiconductor technology advances to nanometer process nodes, Fin FETs face challenges with the bottom side of the channel region being far from the gate electrode, leading to poor control and scalability issues, while GAA FETs require further improvements to maintain performance.

Innovation Solution

The use of As-containing and carbon-containing epitaxial layers, such as SiAs, SiC, SiCAs, and SiCP, as diffusion barriers and caps to prevent phosphorus out-diffusion and improve gate control, combined with a high phosphorus concentration SiP body layer to enhance channel controllability and reduce resistivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Fin FET gate structure surrounds the fin on three surfaces, then gate control is improved, but the bottom part of the channel remains far from the gate electrode resulting in poor control

Engineering Contradiction:

Improvegate controlVSAvoidchannel controllability

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent transitions from three-sided gate wrap (Fin FET) to four-sided gate wrap (GAA FET) by adding vertical nanowire structures, enabling the gate to surround the channel region on all sides including the bottom, thus achieving full gate control through dimensional enhancement

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If transistor dimensions are scaled down to sub 10-15 nm technology nodes, then device density and performance are improved, but short-channel effects increase and require further improvements

Engineering Contradiction:

Improvedevice densityVSAvoidshort-channel effects

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent employs composite material structures including stacked nanowires made of different semiconductor materials (e.g., Si/SiGe, III-V materials) with varying bandgaps and carrier mobilities, allowing optimization of both scaling performance and short-channel effect suppression through material composition design

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses phosphorus diffusion, enhances gate control, and improves scalability and performance of GAA FETs by forming a P diffusion barrier and maintaining low source/drain resistance.

Implementation Method 1

The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer, a SiCAs layer and a SiCP layer

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

a first epitaxial layer is formed over a source/drain region, a second epitaxial layer is formed over the first epitaxial layer and a third epitaxial layer is formed over the second epitaxial layer

Methodology Applied

Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS11101360B2Method of manufacturing a semiconductor device and a semiconductor device

Publication Date: 2021.08.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device includes a channel region, a source/drain region adjacent to the channel region, and a source/drain epitaxial layer. The source/drain epitaxial layer includes a first epitaxial layer epitaxially formed on the source/drain region, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer. The first epitaxial layer includes at least one selected from the group consisting of a SiAs layer, a SiC layer and a SiCP layer.