Gate-All-Around Transistor Fin Tunneling for Parasitic Capacitance Reduction
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Solution Overview
Problem
Fabricating nanosheet-based gate-all-around (GAA) transistors on bulk substrates is challenging due to difficulties in controlling transistor characteristics, particularly unwanted parasitic capacitance between the substrate and source/drain and channel regions, which degrades circuit performance and consumes power.
Innovation Solution
A method involving the formation of elongated, high aspect-ratio fins over a substrate, where a section is removed to create a tunnel separating the fin into active and inactive regions, with a gate structure wrapping around the active fin region to increase electrical conductivity and reduce parasitic coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanosheet-based GAA transistors are fabricated on bulk substrates, then device density and channel control are improved, but parasitic capacitance between substrate and source/drain increases
Solution Approach 1:
The fin is segmented into active upper fin region and inactive lower fin region by removing a portion to form a fin tunnel. This segmentation separates the channel-forming region from the substrate-contacting region, allowing the lower fin region to be electrically isolated from the substrate while the upper fin region forms the functional channel, thus reducing parasitic capacitance while maintaining device density
Solution Approach 2:
A portion of the fin is extracted/removed to create the fin tunnel. This extracted portion serves as the isolation region that prevents direct electrical contact between the substrate and the active channel region, thereby eliminating the parasitic capacitance pathway while preserving the beneficial high-density GAA transistor structure
2Manufacturing precision
If the fin aspect ratio is increased to improve gate control, then channel control is improved, but manufacturing complexity increases
Solution Approach 1:
The fin structure is divided into distinct active and inactive regions separated by the fin tunnel. This segmentation allows the upper active region to achieve high aspect ratio for superior gate control, while the lower inactive region provides a broader base for manufacturing stability, effectively decoupling the conflicting requirements
Solution Approach 2:
Different regions of the fin are assigned different functions: the upper fin region is optimized for electrical performance with high aspect ratio and thin oxide for strong gate control, while the lower fin region is optimized for mechanical stability and electrical isolation. This local differentiation resolves the contradiction between high aspect ratio needs and manufacturing complexity
Data Source
AI summary
Embodiments of the invention are directed to a semiconductor-based structure. A non-limiting example of the semiconductor-based structure includes a fin formed over a substrate. A tunnel is formed through the fin to define an upper fin region and a lower fin region. A gate structure is configured to wrap around a circumference of the upper fin region.