Gate-All-Around Transistor Fabrication with Uniform Gate Electrode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate-all-around transistors (GAATs) suffer from non-uniform gate electrode layers and leakage currents due to residual sacrificial layers, leading to parasitic channel formation and material degradation in semiconductor devices.
Innovation Solution
A semiconductor device with a gate electrode layer of uniform thickness is fabricated by forming a partial insulation layer and a gate insulation layer, ensuring the gate electrode layer surrounds the channel layer without underlying formation of parasitic channels, and a method involving sequential layer formation and etching processes to prevent leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional gate-all-around transistor (GAAT) is fabricated using a sacrificial layer, then the gate electrode layer can surround the channel layer, but the gate electrode layer becomes non-uniform in thickness and leakage currents occur due to residual sacrificial layers
Solution Approach 1:
The patent removes the sacrificial layer completely after forming the gate electrode layer, eliminating residual sacrificial material that causes leakage currents. The gate electrode layer is formed to surround the channel layer, then the sacrificial layer is extracted through etching processes, ensuring no remnants remain on source and drain regions.
Solution Approach 2:
The gate electrode layer is formed in advance to completely surround the channel layer before removing the sacrificial layer. This preliminary formation ensures uniform thickness is achieved while the subsequent sacrificial layer removal eliminates leakage paths without affecting the already-formed uniform gate structure.
2Productivity
If the channel width is decreased to achieve higher integration, then the design rule is improved, but the short channel effect and narrow channel effect worsen
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that surround the channel layer vertically and laterally. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects even at reduced channel widths required for high integration.
3Ease of manufacture
If a sacrificial layer is used to form the gate-all-around structure, then the gate electrode can encompass the channel layer, but parasitic channels form on the gate electrode and substrate
Solution Approach 1:
The patent uses the sacrificial layer's temporary presence to enable precise formation of the gate-all-around structure, then removes it completely to eliminate parasitic channel formation. The sacrificial layer serves its beneficial purpose during manufacturing, then its complete removal converts the potential harm of residual material into a benefit by preventing parasitic channels.
Solution Approach 2:
The patent employs selective etching parameters and processes that completely remove the sacrificial layer without affecting the gate electrode layer or channel layer. By controlling etch selectivity and depth parameters, the sacrificial layer is entirely eliminated, preventing parasitic channel formation while preserving the desired gate-all-around structure.
Data Source
AI summary
A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.