Gain-Boosted Dynamic Comparator for Low-Noise SAR ADCs
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Solution Overview
Problem
Conventional two-stage dynamic comparators have limited gain, which affects noise performance and efficiency in high-speed applications like high-resolution SAR ADCs.
Innovation Solution
A dynamic comparator design with a dynamic amplifier and latch circuit, incorporating a gain-boosting circuit and dual input pairs, where transistors with different conductivity types (NMOS and PMOS) operate in saturation regions at different phases to enhance gain and extend the amplification period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional two-stage dynamic comparator is used, then the comparator can operate at low supply voltage and high speed, but the gain is limited which lowers noise performance
Solution Approach 1:
The patent applies dynamics by making the transconductance of the input pair time-varying through clocked control. The input pair operates in different regions (linear vs saturation) during different phases of the clock cycle, dynamically adjusting the gain characteristics to achieve both high speed and high gain performance
Solution Approach 2:
The patent changes the operating parameter (transconductance) of the input pair by controlling its region of operation. By switching between linear and saturation regions through clocked control, the system achieves variable gain that improves both noise performance and speed
2Measurement precision
If the amplifier gain is increased to improve noise performance, then the noise performance improves, but the amplification duration is reduced which affects speed
Solution Approach 1:
The patent uses periodic clocked action to control the amplifier operation. The amplifier is activated during specific phases of the clock cycle to provide high gain when needed, then deactivated or switched to different operating modes to maintain speed performance, creating a periodic amplification pattern that balances gain and duration
Solution Approach 2:
The system dynamically switches the amplifier between different operating states (high gain mode vs. speed mode) based on the clock phase, achieving time-varying characteristics that resolve the contradiction between amplification duration and noise performance
Data Source
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AI summary
The present invention provides a dynamic comparator (700) including a dynamic amplifier (710) and a latch circuit (720, 730). The dynamic amplifier includes a first input pair (M11, M12), a current source (M13) and a gain boosting circuit (M14, M15). The first input pair is configured to receive an input signal (Vip, Vin) to generate an amplified signal (Von, Vop) at an output terminal (N1, N2). The current source is coupled between the first input pair and a first reference voltage (AVss). The gain-boosting circuit (M14, M15) is coupled between the first input pair (M11, M12) and a second reference voltage (AVdd), and is configured to receive the input signal to selectively inject current to the output terminal or sink current from the output terminal. The latch circuit (720, 730) is coupled to the dynamic amplifier (710), and is configured to receive the amplified signal (Von, Vop) to generate an output signal (Voutn, Voutp).