Gain Cell Feedback for Leakage-Resistant Memory
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Solution Overview
Problem
Modern microprocessors and VLSI systems-on-chip with aggressively scaled CMOS technologies face high leakage currents, leading to increased power consumption and unreliable embedded memory performance, especially in ultra-low power applications, where conventional SRAM bitcells become unreliable at near-threshold operating voltages and exhibit short data retention times due to high leakage currents.
Innovation Solution
The introduction of gain cells with internal feedback mechanisms, specifically four-transistor, five-transistor, and six-transistor configurations, that selectively protect the weaker data level through a conditional feedback path, reducing the need for frequent refresh cycles and lowering power consumption by disconnecting the buffer node from the constant voltage during retention of the stronger data level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 6T SRAM bitcells are used in scaled CMOS nodes, then fast access speed and robust data retention are achieved, but silicon area consumption and leakage power increase significantly
Solution Approach 1:
The memory cell is segmented into distinct functional blocks: write element (transistors 202, 204), retention element (transistors 206, 208), and read element (transistor 210). This segmentation allows each component to be optimized independently for its specific function, achieving reliable data retention with reduced area compared to conventional 6T SRAM.
2Use of energy by stationary object
If supply voltage is scaled down to sub-threshold region to reduce power consumption, then static and dynamic power dissipation decrease, but conventional 6T SRAM becomes unreliable
Solution Approach 1:
The retention element provides cell-internal feedback by connecting the buffer node (203) to the storage node (205) through transistor 206. This feedback mechanism actively compensates for leakage currents and maintains data integrity even at sub-threshold voltages, enabling reliable operation with minimal power consumption.
Solution Approach 2:
The retention element continuously prepares the storage node by maintaining the buffer node voltage through feedback, preventing data degradation before it occurs. This preliminary action ensures data readiness without requiring frequent refresh cycles, reducing overall power consumption at ultra-low voltages.
3Area of stationary object
If conventional 2T gain cells are used in 65 nm technology, then smaller area is achieved, but data retention time decreases to only tens of microseconds
Solution Approach 1:
The buffer node (203) acts as an intermediary between the write element and storage node, providing voltage conditioning and isolation. This intermediary structure enables the retention element to effectively maintain data over extended periods while keeping the cell area small, achieving retention times of tens to hundreds of milliseconds in 65 nm technology.
4Reliability
If one data level is retained in the gain cell, then the other data level deteriorates faster due to higher leakage currents
Solution Approach 1:
The retention element applies localized quality control by selectively strengthening the weaker data level through feedback. The buffer node voltage is adjusted based on the storage node state, providing targeted compensation to the vulnerable data level while leaving the stronger level unchanged, thus balancing retention times for both data levels.
Data Source
AI summary
A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.