Transistor Gain Cell Feedback for Data Retention
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Solution Overview
Problem
Modern microprocessors and VLSI systems-on-chip with high leakage currents require significant embedded memory, leading to increased silicon area and power consumption, with gain-cell embedded DRAMs needing frequent power-hungry refresh cycles for data retention, while conventional gain cells exhibit asymmetric data retention times due to varying leakage currents.
Innovation Solution
A four-transistor gain cell with internal feedback, featuring a retention element with two switching elements that buffers between write and read transistors during data retention, selectively connecting to a constant voltage to protect the weaker data level, reducing the need for frequent refresh cycles and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional 2T gain cells are used in newer technology nodes, then device complexity is reduced, but data retention time deteriorates significantly due to higher leakage currents
Solution Approach 1:
The patent implements a feedback mechanism where the retention element monitors the data level at its input and selectively applies feedback to the write transistor gate. When the stored data level decays below a threshold, the feedback mechanism activates to restore the level, thereby extending data retention time without requiring additional transistors beyond the basic 2T gain cell structure.
Solution Approach 2:
The retention element changes the operating parameters of the write transistor by applying feedback voltage to its gate. This dynamic parameter adjustment allows the write transistor to function as a retention element, compensating for leakage currents and extending data retention time while maintaining the original 2T cell structure.
2Reliability
If refresh cycles are increased to maintain data retention in gain-cell embedded DRAMs, then data reliability is improved, but power consumption increases significantly
Solution Approach 1:
The retention element operates autonomously by continuously monitoring the data level at its input and self-correcting when decay is detected. This self-service mechanism eliminates the need for external refresh controllers and periodic refresh cycles, significantly reducing refresh power consumption while maintaining data retention reliability.
Solution Approach 2:
The feedback mechanism provides continuous monitoring and correction of data levels, replacing the need for periodic refresh operations. By detecting and compensating for data level decay in real-time, the system maintains reliability without the power-hungry refresh cycles required by conventional GC-eDRAM architectures.
3Device complexity
If asymmetric data retention is accepted in conventional gain cells, then device complexity is reduced, but one data level deteriorates much faster requiring higher refresh frequencies
Solution Approach 1:
The feedback mechanism symmetrically addresses both data levels (0 and 1) by monitoring the retention element input and applying corrective feedback to the write transistor gate when either level decays. This eliminates the asymmetric retention behavior of conventional gain cells, where one data level typically deteriorates faster than the other, thereby improving overall reliability without increasing circuit complexity.
Data Source
Figure 1A~1B
Figure 2
Figure 3~4
AI summary
A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.