Gain Cell Memory Sensing via Dynamic Source Bias
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Solution Overview
Problem
Gain cell memory devices face challenges in maintaining effective charge retention time and efficient data refresh rates without increasing device size or power consumption.
Innovation Solution
The solution involves enhancing the conducting state of the read transistor by biasing its source region with a specific voltage, reducing resistive load on the read bit line, and optimizing the output voltage to differentiate marginal charge states, thereby improving sensitivity and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read transistor conducting state is enhanced by biasing the source region with a specific voltage, then the sensitivity and charge retention time are improved, but the device complexity and power consumption may increase
Solution Approach 1:
The patent applies parameter changes by biasing the source region of the read transistor with a specific voltage (different from the normal source bias voltage) to enhance the conducting state. This voltage parameter modification increases the on-current, thereby improving sensitivity and charge retention time without requiring additional device structures
2Measurement precision
If the resistive load on the read bit line is reduced and output voltage is optimized, then the sensitivity for differentiating marginal charge states is improved, but the device complexity increases
Solution Approach 1:
The patent optimizes sensitivity by modifying electrical parameters: reducing the resistive load on the read bit line and adjusting the output voltage to specific levels. These parameter changes enable better differentiation of marginal charge states without adding physical device structures
Solution Approach 2:
The patent employs dynamic biasing where the source region voltage is changed specifically during read operations to enhance conducting state temporarily. This dynamic parameter adjustment provides high sensitivity only when needed, avoiding continuous complexity
3Duration of action of stationary object
If the effective charge retention time is extended, then the data refresh rate is reduced, but the device size may increase
Solution Approach 1:
The patent extends charge retention time by changing the electrical parameters of the read transistor (source bias voltage) and the read bit line (resistive load). These parameter modifications enhance the sensing capability and retention characteristics without requiring larger physical dimensions of the memory cell
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach extends the effective charge retention time, reduces data refresh rates, and maintains low power operation while ensuring high sensitivity in read operations.
Implementation Method 1
a read transistor RT located on the substrate, wherein the read transistor RT is configured to conduct a drain current Ids from a drain region to a source region
Data Source
AI summary
A gain cell memory device is provided, which includes a write transistor located on a substrate; a read transistor located on the substrate; a capacitor having a first electrode, a node dielectric, and a second electrode, wherein the first electrode is electrically connected to a first source/drain region of the write transistor and to a gate electrode of the read transistor; and a peripheral circuit configured to electrically bias a source region of the read transistor at a normal source bias voltage while the gain cell memory device is not under a read operation, and at a current-boost source bias voltage that increases an on-current of the read transistor while the gain cell memory device is under the read operation.