Gain Update Circuit Timing for Artifact-Free Audio Control
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Solution Overview
Problem
Existing gain control systems in digital audio processing face challenges in synchronizing updates between low- and high-resolution gain stages, leading to signal transients and audible artefacts due to misalignment of gain updates in the signal chain.
Innovation Solution
An integrated circuit (IC) with gain update circuitry that outputs internal and external gain control signals with a predetermined delay to compensate for signal chain latency, using level detection and zero-crossing detection to time-align gain updates with signal events, and incorporates masking signals to mitigate transient effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If digital control of gain is implemented using discrete resistors and switches, then gain can be adjusted in low-resolution steps, but the system cannot easily synchronize updates between low- and high-resolution gain stages
Solution Approach 1:
The patent combines discrete resistor-based gain switching with digital potentiometer control into a unified gain control system. The discrete resistors provide coarse gain steps while the digital potentiometer provides fine-resolution adjustment, and both are controlled through a single digital interface that automatically coordinates their updates to prevent transients.
Solution Approach 2:
The system performs preliminary gain adjustment through the discrete resistor stage before applying fine-resolution adjustment through the digital potentiometer. This staged approach allows the system to prepare the signal path with coarse adjustments first, then apply precise adjustments without causing synchronization issues or audible transients.
2Ease of operation
If gain updates are applied without time-alignment to signal events, then gain control is simpler, but signal transients and audible artefacts occur
Solution Approach 1:
The system uses zero-crossing detection to monitor the signal and provides feedback timing information to the gain control logic. This feedback mechanism allows the system to automatically synchronize gain updates with signal events without complex manual timing, maintaining simplicity while eliminating transients caused by misaligned updates.
Solution Approach 2:
The gain control system updates gain values at periodic signal events (zero-crossings) rather than continuously or at arbitrary times. This periodic update strategy, triggered by natural signal characteristics, ensures smooth transitions without transients while keeping the control logic simple and deterministic.
3Adaptability or versatility
If gain control uses analog potentiometer, then continuous gain variation is achieved, but it cannot be easily controlled by digital means
Solution Approach 1:
The patent replaces the mechanical analog potentiometer with a digital potentiometer that can be controlled through digital interfaces. This substitution maintains the continuous gain adjustment capability of analog controls while enabling integration with digital audio processing systems, allowing gain to be varied continuously through digital commands rather than mechanical rotation.
Data Source
AI summary
An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage, wherein the gain update circuitry comprises level detection circuitry configured to determine a signal level of the first input signal or the first output signal.