Co-Packaged GaN Transistor and Diode Package
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Solution Overview
Problem
Conventional power electronics face challenges in reducing package size, minimizing electromagnetic interference (EMI), and maintaining high voltage and current ratings, especially when operating at higher frequencies, due to large and heavy package sizes and increased parasitic inductance, resistance, and capacitance.
Innovation Solution
The co-packaging of gallium nitride (GaN) power devices, such as transistors and diodes, into a single electronic package with a vertical architecture, utilizing a leadframe for interconnections, which reduces parasitic effects and allows for smaller, more efficient designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional power electronics packages are used to maintain high voltage and current ratings, then the package size becomes large and heavy, but the goal is to reduce package size
Solution Approach 1:
The patent combines multiple power devices (GaN transistor and GaN diode) into a single integrated power module package. The leadframe structure integrates multiple device mounting areas, electrical interconnections, and thermal management pathways within one compact package, eliminating the need for separate packages for each device while maintaining high voltage and current handling capabilities through optimized internal architecture.
Solution Approach 2:
The patent employs a vertical device architecture where current flow and electrical connections are optimized in the vertical dimension rather than lateral expansion. The leadframe and internal interconnections are designed to utilize vertical space efficiently, allowing high power ratings to be achieved without increasing the horizontal package footprint, thus reducing overall package volume.
2Reliability
If conventional packages are used to achieve high power ratings, then parasitic inductance, resistance, and capacitance increase, but the goal is to reduce parasitic effects
Solution Approach 1:
The patent extracts and minimizes parasitic elements by optimizing the leadframe design and internal interconnection pathways. The leadframe structure is specifically designed to reduce loop areas and interconnection lengths, thereby extracting harmful parasitic inductance and resistance from the overall system. The compact integration removes unnecessary external connection paths that would contribute to parasitic effects.
Solution Approach 2:
The patent applies different structural optimizations to different regions of the package. The leadframe and interconnection structures are designed with local quality variations - for example, thicker trace widths and optimized via structures in high-current regions to reduce resistance, and minimized loop areas in high-dI/dt regions to reduce parasitic inductance. This localized optimization reduces parasitic effects without compromising overall power performance.
3Speed
If conventional silicon circuits are operated at higher frequencies, then power loss and EMI increase, but the goal is to operate at higher frequencies with reduced power loss and EMI
Solution Approach 1:
The patent changes the fundamental material parameter from conventional silicon to gallium nitride (GaN) semiconductor technology. GaN's superior material properties - including higher electron mobility, wider bandgap, and higher breakdown field - enable the devices to operate at much higher frequencies with lower conduction losses and reduced switching losses. This material parameter change fundamentally enables high-frequency operation while reducing power loss and electromagnetic interference compared to silicon-based solutions.
Data Source
AI summary
An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe.