SiN Passivation Layer for GaN Transistors
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Solution Overview
Problem
The existing passivation schemes for GaN transistors, such as LPCVD or MOCVD SiN layers, compromise dynamic performance, and high temperature processes can delaminate SiN passivation layers, leading to reduced yield and performance in semiconductor manufacturing.
Innovation Solution
A combination SiN passivation layer is formed by depositing a first SiN layer with tensile stress at a higher temperature (above 600°C) and a second SiN layer with compressive stress at a lower temperature (below 400°C), which are then used to create a stable passivation layer resistant to high temperature manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PECVD SiN passivation layer is deposited at low temperature (below 400°C), then the dynamic performance is maintained, but the adhesion is poor and delamination occurs during high temperature processing
Solution Approach 1:
The patent divides the SiN passivation layer into multiple sub-layers with different deposition temperatures and compositions. The first SiN layer is deposited at high temperature (600-800°C) to provide strong adhesion, while the second SiN layer is deposited at low temperature (below 400°C) to maintain dynamic performance. This segmentation allows each layer to optimize for its specific function, resolving the contradiction between adhesion and temperature.
Solution Approach 2:
The patent creates a composite SiN passivation structure combining layers with different properties. The high-temperature SiN layer provides adhesion and thermal stability, while the low-temperature SiN layer provides passivation quality and dynamic performance. This composite approach integrates the advantages of both high and low temperature deposition, resolving the contradiction between adhesion strength and device performance.
2Ease of manufacture
If high temperature process steps are conducted after SiN passivation layer formation, then gate insulator can be deposited, but the SiN passivation layer delaminates from AlGaN layer
Solution Approach 1:
The patent performs preliminary high-temperature processing to deposit the first SiN layer with strong adhesion before subsequent low-temperature gate insulator deposition. This preliminary action creates a thermally stable foundation that can withstand subsequent manufacturing steps, preventing delamination while allowing gate insulator formation.
Solution Approach 2:
The patent changes the deposition temperature parameter for different SiN layers. The first SiN layer is deposited at high temperature (600-800°C) to achieve thermal stability and strong adhesion, while the second SiN layer is deposited at low temperature (below 400°C) to preserve passivation quality. This parameter differentiation resolves the contradiction between manufacturing ease and layer integrity.
3Stability of the object's composition
If LPCVD or MOCVD SiN layer is used for passivation, then temperature stability increases, but dynamic performance is compromised
Solution Approach 1:
The patent segments the passivation function across two SiN layers with different deposition methods and temperatures. The first SiN layer (high temperature) provides thermal stability and adhesion, while the second SiN layer (low temperature PECVD) provides optimal passivation quality and dynamic performance. This segmentation allows each layer to specialize in one aspect, resolving the contradiction between temperature stability and dynamic performance.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the passivation structure. The first SiN layer has high thermal stability and adhesion properties, while the second SiN layer has superior passivation quality for maintaining dynamic performance. Each layer is optimized for its local function, resolving the contradiction between temperature stability and device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The combination SiN passivation layer significantly improves stability and resistance to high temperature processes, preventing delamination and maintaining performance and yield in GaN transistor manufacturing.
Implementation Method 1
a first layer of SiN is formed on said at least a portion of said layer of a III-N material by depositing said first layer of SiN on said at least a portion of said layer of a III-N material
Implementation Method 2
a second layer of SiN is formed on said first layer of SiN by depositing said second layer of SiN on said first layer of SiN
Data Source
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AI summary
A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.