Lateral Gallium Oxide Transistor With Nickel Diffusion Barrier
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Solution Overview
Problem
The development of high-performance power semiconductor devices is hindered by the difficulties in bulk single crystal growth and high production costs of ultra-wideband semiconductors like silicon carbide and gallium nitride, while gallium oxide, with a high bandgap and breakdown field, faces challenges in implementing a pn homojunction-based β-Ga2O3 device due to large effective hole mass and high acceptor activation energy.
Innovation Solution
A lateral gallium oxide transistor is designed with a gallium oxide substrate, an n-type gallium oxide epitaxial layer, an insulating layer, a diffusion barrier layer, a p-type nickel oxide layer, and electrodes, where the diffusion barrier layer forms a pn heterojunction to prevent nickel diffusion and maintain low channel resistance, and counter doped regions are formed to adjust dopant concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pn homojunction-based β-Ga2O3 device is implemented, then the device can utilize the high bandgap and breakdown field properties of gallium oxide, but the large effective hole mass and high acceptor activation energy make it difficult to achieve proper p-type doping and junction formation
Solution Approach 1:
The patent introduces a diffusion barrier layer as an intermediary between the p-type nickel oxide layer and the n-type gallium oxide epitaxial layer. This barrier layer prevents nickel diffusion into the channel region while still allowing the formation of a pn heterojunction, thereby solving the doping difficulty without compromising device performance
Solution Approach 2:
The patent changes the doping approach by using nickel oxide with controlled oxygen content rather than traditional p-type dopants. By adjusting the oxygen content in nickel oxide, the patent achieves proper p-type characteristics despite the challenging material properties of gallium oxide
2Reliability
If the diffusion barrier layer is made thicker to prevent nickel diffusion, then nickel diffusion is better blocked, but the formation of the pn heterojunction is hindered
Solution Approach 1:
The patent optimizes the thickness parameter of the diffusion barrier layer to a specific range (2 Å to 50 Å) where it provides sufficient nickel diffusion blocking while still allowing adequate charge carrier transport for heterojunction formation. This precise parameter control resolves the contradiction between diffusion prevention and junction formation
3Ease of manufacture
If gallium oxide is used instead of silicon carbide or gallium nitride, then production costs are reduced and substrate growth is easier, but the large effective hole mass and high acceptor activation energy create difficulties in implementing pn homojunction devices
Solution Approach 1:
The patent creates a composite structure combining multiple materials (gallium oxide substrate, n-type gallium oxide epitaxial layer, diffusion barrier layer, p-type nickel oxide layer) to achieve the desired device functionality. This composite approach allows utilization of gallium oxide's cost advantages while compensating for its doping difficulties through carefully selected material combinations
Solution Approach 2:
The patent transitions from a planar pn homojunction to a vertical pn heterojunction structure with multiple functional layers. This dimensional and structural change allows the device to overcome the limitations of bulk gallium oxide doping while maintaining the material's cost advantages
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of a lateral gallium oxide transistor with controlled channel resistance, allowing for efficient operation and potentially lower production costs compared to other ultra-wideband semiconductor materials.
Implementation Method 1
the diffusion barrier layer may be deposited at a thickness such that a pn heterojunction is formed between the p-type nickel oxide layer and the n-type gallium oxide epitaxial layer while preventing nickel diffusion from the p-type nickel oxide layer to the n-type gallium oxide epitaxial layer
Implementation Method 2
a pn heterojunction is formed between the p-type nickel oxide layer and the n-type gallium oxide epitaxial layer
Implementation Method 3
an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate
Data Source
AI summary
Lateral gallium oxide transistor includes a gallium oxide substrate, an n-type gallium oxide epitaxial layer epitaxially grown on the gallium oxide substrate, an insulating layer defining a gate region, a source region, and a drain region on the n-type gallium oxide epitaxial layer, a diffusion barrier layer deposited on the n-type gallium oxide epitaxial layer exposed in the gate region, a p-type nickel oxide layer deposited on the diffusion barrier layer, a dielectric layer deposited on the p-type nickel oxide layer, a gate electrode layer deposited on the dielectric layer, and a source electrode and a drain electrode formed on the n-type gallium oxide epitaxial layer exposed in the source region and the drain region.