Gallium Oxide Ohmic Contact Structure Using ITO Diffusion Layer
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Solution Overview
Problem
The development of high-performance power semiconductor devices is hindered by the challenges of difficult bulk single crystal growth and high production costs associated with ultra-wideband semiconductors like silicon carbide and gallium nitride. Additionally, gallium oxide, while promising, faces difficulties in implementing a pn homojunction-based β-Ga2O3 device due to large effective hole mass and high acceptor activation energy of p-type dopants.
Innovation Solution
A gallium oxide semiconductor device is proposed, featuring an n-type gallium oxide epitaxial layer grown on a gallium oxide substrate, an n-type contact layer of indium tin oxide, a metal electrode layer, and a diffusion layer formed by post-annealing. This configuration includes a p-type nickel oxide layer, a dielectric layer, and a gate electrode layer, with a diffusion barrier layer preventing nickel diffusion and allowing the formation of a pn heterojunction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a pn homojunction-based β-Ga2O3 device is implemented, then device functionality is achieved, but the large effective hole mass and high acceptor activation energy of p-type dopants prevent successful implementation
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the p-type and n-type regions, enabling device operation without requiring functional p-type doping. This mediator allows the system to achieve pn junction functionality through alternative means, bypassing the material limitations of p-type gallium oxide.
Solution Approach 2:
The patent changes the fundamental operating parameters by transitioning from a homojunction to a heterojunction structure, and from relying on p-type doping to using insulating layers with controlled breakdown characteristics. This parameter change enables device functionality despite the unsuitability of p-type dopants in gallium oxide.
2Reliability
If ultra-wideband semiconductor materials like silicon carbide and gallium nitride are used, then higher performance is achieved, but bulk single crystal growth becomes difficult and production costs increase
Solution Approach 1:
The patent employs gallium oxide, a lower-cost alternative to silicon carbide and gallium nitride, accepting that while the material itself is less expensive and easier to manufacture, the device achieves comparable performance through innovative structural design rather than relying on expensive bulk materials.
Solution Approach 2:
The patent creates a composite device structure combining gallium oxide with insulating materials having different breakdown characteristics, achieving ultra-wideband performance through material composition and structure rather than relying solely on the intrinsic properties of expensive bulk semiconductors.
3Reliability
If the n-type contact layer thickness is reduced to 10 nm to 30 nm, then ohmic contact properties are enhanced, but the contact layer becomes more difficult to control during fabrication
Solution Approach 1:
The patent optimizes the contact layer thickness to a specific range (10-30 nm) that balances ohmic contact performance with manufacturability. This parameter optimization achieves low contact resistance while remaining within the capabilities of standard fabrication processes, rather than pushing to extreme thinness that would compromise manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described gallium oxide semiconductor device achieves improved electrical characteristics, including reduced contact resistance and enhanced ohmic contact properties, thereby addressing the challenges of high production costs and material limitations in existing semiconductor technologies.
Implementation Method 1
a diffusion layer extending from a heterojunction between the n-type gallium oxide epitaxial layer and the n-type contact layer toward the n-type gallium oxide epitaxial layer. The diffusion layer may be formed by diffusing the n-type contact layer into the n-type gallium oxide epitaxial layer by a post-annealing.
Implementation Method 2
The diffusion layer may be formed by diffusing the n-type contact layer into the n-type gallium oxide epitaxial layer by a post-annealing.
Implementation Method 3
a diffusion barrier layer, interposed between the n-type gallium oxide epitaxial layer exposed in the gate region and the p-type nickel oxide layer.
Data Source
AI summary
Gallium oxide semiconductor device may include an n-type gallium oxide epitaxial layer epitaxially grown on a gallium oxide substrate, an n-type contact layer formed of indium tin oxide on the n-type gallium oxide epitaxial layer, a metal electrode layer formed on the n-type contact layer, and a diffusion layer extending from a heterojunction between the n-type gallium oxide epitaxial layer and the n-type contact layer toward the n-type gallium oxide epitaxial layer. The diffusion layer may be formed by diffusing the n-type contact layer into the n-type gallium oxide epitaxial layer by a post-annealing.