Gallium-Enriched P-Type Transistor Contacts for Low Contact Resistivity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors scale to smaller dimensions, maintaining suitable contact resistivity at the source/drain interface becomes challenging, with existing techniques only partially reducing contact resistivity to desired levels, particularly when a single active dopant like boron is present at the silicide interface.
Innovation Solution
Incorporating a gallium enriched layer between the source/drain material and the contact metal, where the gallium is epitaxially grown and incorporated in the range of 5E19 to 5E20 atoms/cm^3, increasing the total carrier concentration and reducing contact resistivity below 1E-9 Ohms-cm^2.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled to smaller dimensions, then device density and integration are improved, but contact resistivity at the source/drain interface increases
Solution Approach 1:
The patent applies local quality by creating a gallium-enriched layer specifically at the contact interface region where high conductivity is needed, while maintaining the original semiconductor composition in the bulk source/drain regions. This localized modification targets the specific problem area (contact resistivity) without affecting the overall device structure and enables smaller transistor dimensions while maintaining low contact resistance.
Solution Approach 2:
The patent changes the compositional parameter by introducing gallium enrichment at the contact interface, which fundamentally alters the electrical properties of that specific region. The gallium concentration is controlled to achieve optimal carrier concentration and reduce contact resistivity, demonstrating parameter change as a solution to the scaling contradiction.
2Ease of manufacture
If a single active dopant like boron is used at the silicide interface, then doping process is simplified, but contact resistivity reduction is insufficient
Solution Approach 1:
The patent employs composite materials by combining boron-doped silicon germanium with a gallium-enriched layer at the contact interface. This composite structure leverages the electrical activation properties of boron while adding the conductivity enhancement from gallium enrichment, achieving superior contact resistivity reduction compared to single-dopant approaches.
Solution Approach 2:
The gallium-enriched layer acts as an intermediary between the boron-doped silicon germanium source/drain region and the metal contact. This intermediate layer mediates the electrical interface, providing a transition zone with enhanced carrier concentration that facilitates better charge transport and reduces contact resistivity.
3Reliability
If carrier concentration at the contact surface is increased, then contact resistivity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies partial action by introducing gallium enrichment to a limited depth at the contact interface rather than throughout the entire source/drain region. The gallium-enriched layer is confined to a thin region (typically nanometer scale) at the surface, providing the necessary carrier concentration enhancement while minimizing the complexity of controlling gallium distribution throughout the bulk material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The gallium enriched layer effectively reduces contact resistivity to below 1E-9 Ohms-cm^2, improving transistor performance by enhancing carrier concentration at the source/drain contact surface.
Implementation Method 1
the gallium is epitaxially grown and incorporated in the range of 5E19 to 5E20 atoms/cm^3
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 3A~3C
AI summary
In some implementations, an apparatus may include a substrate (218) having silicon. In addition, the apparatus may include a first layer of a source or drain region (225) of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer (217) coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer (219) positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.