Gallium-Enriched Transistor Contacts for Lower Source-Drain Resistivity

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Solution Overview

Problem

As transistors scale to smaller dimensions, maintaining suitable contact resistivity at the source/drain interface becomes challenging, with existing techniques only reducing contact resistivity to around 1.5E-9 Ohms-cm2, which is not sufficient for optimal transistor performance.

Innovation Solution

Incorporating a gallium enriched layer between the source/drain material and the contact metal, specifically using epitaxially grown boron doped silicon germanium exposed to a metallo-organic precursor containing gallium, to increase the carrier concentration and reduce contact resistivity below 1E-9 Ohms-cm2.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing techniques are used to reduce contact resistivity, then contact resistivity can be reduced to around 1.5E-9 Ohms-cm2, but this is not sufficient for optimal transistor performance at smaller dimensions

Engineering Contradiction:
Improvecontact resistivityVSAvoidtransistor performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by creating a gallium-enriched layer specifically at the contact interface region where it is most needed. This localized modification of composition (enriching with gallium atoms) occurs only in the source/drain contact regions rather than throughout the entire transistor structure, thereby reducing contact resistivity locally without affecting other transistor performance parameters globally

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the chemical composition parameter of the source/drain material by incorporating gallium atoms into the crystal structure. This parameter change (adding gallium enrichment) modifies the electrical properties of the contact region, increasing carrier concentration and reducing contact resistivity below 1E-9 Ohms-cm2, thereby resolving the contradiction between existing technique limitations and optimal transistor performance requirements

Inventive Principle:
Principle #35Parameter changes

2Volume of moving object

If transistors are scaled to smaller dimensions, then device size is reduced, but maintaining suitable contact resistivity becomes increasingly challenging

Engineering Contradiction:
Improvetransistor sizeVSAvoidcontact resistivity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

As transistors scale to smaller dimensions, the patent applies local quality by concentrating gallium enrichment specifically at the contact interfaces where resistivity control is most critical. This localized approach ensures that even in miniaturized devices, the contact regions maintain optimal electrical properties without requiring proportional scaling of the entire device structure

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent creates a composite material structure by combining silicon germanium with gallium enrichment at the contact regions. This composite approach (silicon germanium base material plus gallium enrichment layer) provides tailored properties: the silicon germanium provides the semiconductor functionality while the gallium-enriched regions provide enhanced electrical contact properties, enabling reliable operation in scaled-down transistor dimensions

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The gallium enriched layer effectively reduces contact resistivity, enhancing transistor performance by increasing the total carrier concentration at the source/drain contact surface, thereby improving the maximum achievable clock frequency in devices.

Implementation Method 1

increase the carrier concentration and reduce contact resistivity below 1E-9 Ohms-cm2

Methodology Applied
Scientific EffectCarrier concentration increase:

Implementation Method 2

specifically using epitaxially grown boron doped silicon germanium exposed to a metallo-organic precursor containing gallium

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 3

exposed to a metallo-organic precursor containing gallium

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS20250006806A1High conductivity transistor contacts comprising gallium enriched layer
Publication Date: 2025.01.02 INTEL CORP
  • US20250006806A1 patent drawing
  • US20250006806A1 patent drawing
  • US20250006806A1 patent drawing

AI summary

In some implementations, an apparatus may include a substrate having silicon. In addition, the apparatus may include a first layer of a source or drain region of a p-type transistor, the first layer positioned above the substrate, the first layer having boron, silicon and germanium. The apparatus may include a second layer coupled to the source or drain region, the second layer having a metal contact for the source or drain region. Moreover, the apparatus may include a third layer positioned between the first layer and the second layer, the third layer having at least one monolayer having gallium, where the third layer is adjacent to the first layer.