Galois Field Arithmetic Circuitry for Memory Error Correction
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Solution Overview
Problem
As the number of error-correctable bits increases in memory systems using error correction codes like BCH codes, the number of required multiplications in Galois fields increases, leading to a scaling issue in arithmetic circuitry for error locator polynomial calculations.
Innovation Solution
An arithmetic circuitry is configured to efficiently calculate multiplications by using a connected tensor obtained from a set of tensors, optimizing the AND and XOR operations to reduce the circuit scale, allowing for common calculations of syndrome multiplications in error locator polynomial coefficient calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of error-correctable bits increases, then the error correction capability improves, but the number of required Galois field multiplications increases leading to larger circuit scale
Solution Approach 1:
The patent segments the Galois field multiplication operation into distinct computational stages: syndrome calculation, error locator polynomial coefficient calculation, and error position determination. By dividing the multiplication tasks across these segments and identifying redundant operations within each segment, the circuit can reuse computation results rather than performing duplicate multiplications, thus reducing the overall circuit scale while maintaining error correction capability for a higher number of bits
Solution Approach 2:
The patent creates a universal arithmetic circuit that performs multiple functions: it calculates syndromes, computes error locator polynomial coefficients, and determines error positions. This multi-functional circuit design allows the same hardware resources to be reused across different stages of the error correction process, reducing the need for separate dedicated circuits for each function and thereby suppressing the increase in circuit scale as error correction capability increases
2Reliability
If the number of error-correctable bits increases, then the error correction capability improves, but the transistor count in the arithmetic circuitry increases
Solution Approach 1:
The patent merges the arithmetic operations for syndrome calculation, error locator polynomial coefficient calculation, and error position determination into a single integrated arithmetic circuit. By combining these previously separate functions into one unified circuit structure, the patent reduces the total transistor count compared to having separate circuits for each function, while still providing error correction for an increased number of bits
3Measurement precision
If more Galois field multiplications are performed, then the error correction accuracy improves, but the operational efficiency decreases due to larger circuit scale
Solution Approach 1:
The patent performs preliminary calculation of syndromes and error locator polynomial coefficients using optimized arithmetic operations before the actual error position determination. By preparing these intermediate results in advance with reduced computational redundancy, the circuit maintains high error correction accuracy while improving overall operational efficiency, as the subsequent error position calculation can proceed with pre-computed values rather than performing redundant multiplications
Data Source
AI summary
According to one embodiment, an arithmetic circuitry is configured to: calculate an AND value that is a result of an AND operation of elements a and b of a Galois field; and calculate, for each of a plurality of mutually different sets of (u, v), a {circumflex over ( )} (2u)×b {circumflex over ( )} (2v), which is a product of a 2u-th power of a and a 2v-th power of b, from an XOR operation based on the AND value and a connected tensor obtained by collecting a plurality of tensors different for each set.