Galois Field Arithmetic on Programmable Processors
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Solution Overview
Problem
Existing Galois Field arithmetic implementations, particularly in coding theory and encryption, face inefficiencies in processing time and complexity due to the complexity of Galois Field multiplication, which often requires specialized hardware or look-up tables.
Innovation Solution
The introduction of two instructions, gfmul and gfnorm, which split the Galois Field multiply operation into two separate steps, allowing for efficient polynomial multiplication and modulus computation, reducing the need for frequent execution of the modulus operation and optimizing processing time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Galois Field multiplication is implemented using traditional methods (specialized hardware or look-up tables), then processing accuracy is maintained, but processing time increases and processing efficiency decreases
Solution Approach 1:
The patent segments the Galois Field multiplication operation into two distinct instructions: gfmul (polynomial multiplication) and gfnorm (normalization). This segmentation allows the complex multiplication to be broken down into manageable stages, where the expensive modulus operation is performed less frequently. By separating the polynomial multiplication from the normalization step, the system achieves better performance by reducing the frequency of costly modulus operations while maintaining computational accuracy.
Solution Approach 2:
The gfmul instruction performs preliminary polynomial multiplication without immediately applying the modulus operation. This preliminary action accumulates intermediate results that can be processed in batches, allowing the normalization step to be applied less frequently. By deferring the costly modulus operation until necessary, the system reduces overall processing time while maintaining correctness.
2Speed
If Galois Field multiplication uses specialized hardware, then processing speed improves, but device complexity increases
Solution Approach 1:
The patent creates a universal instruction set that can handle Galois Field operations using standard processor components. The gfmul and gfnorm instructions are designed to work with conventional arithmetic logic units and registers, making the processor versatile for both traditional computing tasks and cryptographic operations. This multi-functionality approach eliminates the need for dedicated Galois Field hardware while maintaining processing speed through efficient instruction sequencing.
3Measurement precision
If look-up tables are used for Galois Field multiplication, then processing accuracy is maintained, but memory usage increases and access time is added
Solution Approach 1:
The patent replaces the mechanical approach of look-up table access with an algorithmic approach using the gfmul-gfnorm instruction sequence. Instead of retrieving pre-computed values from memory, the system performs polynomial multiplication followed by normalization using standard arithmetic operations. This substitution eliminates memory access delays and allows for dynamic computation that adapts to different input values without requiring large lookup tables.
Data Source
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AI summary
A method for a Galois Field multiply includes executing first and second instructions. The first inctruction includes receiving a first input, such as a first variable, receiving a second input, such as a second variable, performing a polynomial multiplication over GF(2m), using the first and second inputs, and producing a product. The second instruction includes receiving a third input, which may be the product from the first instruction, receiving a fourth input, which is a predetermined generator polynomial to operate upon the product, receiving a fifth input, which is a length of the predetermined generator polynomial, to limit operation of the predetermined generator polynomial upon the product, and computing, via the predetermined generator polynomial limited by the length, a modulus of the product with respect to a divisor. A hardware block is also described.