Galois-field Reduction Circuitry for Arbitrary Depth and Width
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Solution Overview
Problem
Designing Galois-field operations circuitry for programmable integrated circuit devices is challenging when the sizes of the field and operations are unknown and arbitrary, as existing methods struggle to efficiently perform Galois-field reduction for arbitrary depth and width.
Innovation Solution
The implementation of Galois-field reduction circuitry using a plurality of memories and exclusive-OR gates, which derive and combine values from an irreducible polynomial to reduce expansion values, allowing for cascading of blocks to achieve arbitrary depth and width reductions, and a specialized processing block with a multiplier stage and register file circuitry for performing Galois-field multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed-size reduction circuitry is used, then the circuit is simple and straightforward to build, but it cannot perform Galois-field reductions of arbitrary depth and width
Solution Approach 1:
The reduction circuitry is divided into multiple identical modular blocks, each handling a portion of the reduction. These blocks can be cascaded together to achieve arbitrary depth and width reductions. Each block contains memories storing values derived from the irreducible polynomial and exclusive-OR gates for combining results, creating a scalable architecture that maintains simplicity while achieving versatility.
Solution Approach 2:
Values derived from the irreducible polynomial are precalculated and stored in memories within each block before runtime. This preliminary action allows the circuit to perform reductions efficiently without complex real-time calculations, enabling arbitrary-sized reductions while keeping the operational circuit logic simple and reusable across multiple blocks.
2Adaptability or versatility
If Galois-field reduction circuitry is designed for unknown and arbitrary field sizes, then it can accommodate various user needs, but existing methods struggle to efficiently perform reductions
Solution Approach 1:
Each modular block is designed to be universal and reusable for different field sizes and reduction depths. The same block structure with preconfigured memories and exclusive-OR gates can be instantiated multiple times and cascaded to handle various user needs. This universality allows efficient accommodation of arbitrary field sizes without requiring redesign for each specific application.
Solution Approach 2:
The arbitrary-sized reduction problem is segmented into multiple manageable blocks of fixed size. By dividing the overall reduction task across multiple identical blocks, the system efficiently handles unknown and arbitrary field sizes while maintaining the simplicity and efficiency of fixed-size block operations. The cascaded structure allows linear scaling with the reduction requirements.
Data Source
AI summary
Galois-field reduction circuitry for reducing a Galois-field expansion value, using an irreducible polynomial, includes a plurality of memories, each for storing a respective value derived from the irreducible polynomial and a respective combination of expansion bit values, wherein expansion bits of the expansion value address the plurality of memories to output one or more of the respective values. The Galois-field reduction circuitry also includes exclusive-OR circuitry for combining output of the plurality of memories with in-field bits of said expansion value. There are also a method of operating such Galois-field reduction circuitry to reduce a Galois-field expansion value, a programmable integrated circuit device incorporating the circuitry, a method of performing a Galois-field multiplication operation on such a programmable integrated circuit device, and a method of configuring a programmable integrated circuit device to perform such a Galois-field multiplication operation.