Processor Galois Multiply Circuit for AES Encryption Throughput
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Solution Overview
Problem
Current software-implemented encryption methods for large data sets are inefficient, and hardware solutions like physical encryption engines connected to the memory hierarchy are costly and not applicable to data in flight, necessitating a more effective hardware-based approach for encryption.
Innovation Solution
The implementation of Galois multiplication in hardware through a processor with a carryless multiplier and modular reduction circuit, specifically designed to perform Galois multiply instructions, enhancing encryption performance for AES-GCM and AES-XTS algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If encryption is performed in software on a general purpose processor, then flexibility in selecting encryption functions is improved, but performance is worsened
Solution Approach 1:
The processor is segmented into distinct execution units: a general purpose execution unit for flexible encryption function selection and a dedicated cryptography execution unit for high-performance Galois multiplication operations. This segmentation allows the system to maintain software flexibility while achieving hardware-level performance for critical cryptographic operations.
Solution Approach 2:
The patent introduces an intermediary instruction set architecture layer that includes Galois multiply instructions. These instructions act as intermediaries between the software encryption algorithms and the hardware execution units, enabling the general purpose processor to leverage dedicated cryptography hardware resources while maintaining algorithmic flexibility.
2Productivity
If a physical encryption engine is connected to the memory hierarchy, then encryption performance for data at rest is improved, but cost is worsened
Solution Approach 1:
The cryptography execution unit is integrated into the processor core and can be shared across multiple encryption algorithms and workloads. This multi-functional design eliminates the need for dedicated physical encryption engines for each algorithm, reducing overall system cost while maintaining high performance for Galois multiplication operations used in AES-GCM and AES-XTS.
Solution Approach 2:
The patent merges the cryptography execution unit with the processor core, combining general purpose computing resources with dedicated cryptographic acceleration. This integration eliminates the need for separate physical encryption engines connected to the memory hierarchy, reducing device complexity and cost while providing in-flight encryption capabilities.
3Productivity
If a physical encryption engine is connected to the memory hierarchy, then encryption for data at rest is improved, but applicability to data in flight is worsened
Solution Approach 1:
The patent extracts the cryptography execution unit from the memory hierarchy and integrates it directly into the processor core. This extraction enables the encryption capability to operate on data in flight within the processor pipeline, while still maintaining the ability to handle data at rest through the same integrated unit.
Data Source
AI summary
A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.