GALS Circuit Jitter Generator for EMI Reduction
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Solution Overview
Problem
Complex circuit designs, especially those with mixed analog and digital signals, face challenges in reducing electromagnetic interference (EMI) and power signature analysis, which disrupt performance and security in cryptographic applications.
Innovation Solution
A Globally Asynchronous Locally Synchronous (GALS) circuit with integrated jitter generators that introduce random signal delays to clock and request signals, reducing EMI and making power signature analysis more difficult, thereby facilitating the integration of complex chips with mixed signals and enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If synchronous clocking is used in complex circuit systems, then system integration is simplified, but electromagnetic interference increases and disrupts analog circuit performance
Solution Approach 1:
The circuit system is divided into multiple clock domains, with each domain operating independently with its own clock signal. This segmentation allows digital and analog circuits to be separated into different clock domains, reducing electromagnetic interference from digital clocks to analog circuits while maintaining integration benefits.
Solution Approach 2:
The patent introduces dynamic clock gating mechanisms that selectively enable or disable clock signals to specific circuit blocks based on operational requirements. This dynamic control reduces unnecessary clock switching activity, thereby reducing electromagnetic interference and power consumption while maintaining system integration.
2Use of energy by moving object
If clock gating is used to reduce power consumption, then energy efficiency improves, but clock coordination complexity increases
Solution Approach 1:
The patent employs a universal asynchronous transfer mechanism that can be applied across multiple clock domains and circuit blocks. This universal handshake protocol simplifies clock coordination by providing a standardized method for data transfer between different clock domains, reducing the overall complexity despite using multiple clock gating mechanisms.
Solution Approach 2:
Asynchronous transfer signals act as intermediaries between different clock domains, mediating data transfer without requiring direct clock synchronization. This intermediary mechanism simplifies clock coordination by eliminating the need for complex synchronization logic while enabling effective clock gating for power reduction.
3Object-affected harmful factors
If standard GALS circuits are used, then electromagnetic interference is reduced, but cryptographic security against power analysis attacks is not improved
Solution Approach 1:
The patent introduces random jitter to clock and request signals, dynamically changing the timing parameters of signal transitions. This randomization alters the power consumption profile and electromagnetic radiation characteristics in an unpredictable manner, preventing power analysis attacks while maintaining the EMI reduction benefits of GALS architecture.
Solution Approach 2:
The patent converts the deterministic timing characteristics that could be exploited for power analysis into beneficial randomization. By introducing controlled jitter, the predictable power consumption patterns are transformed into randomized patterns that enhance security, while the overall EMI reduction from asynchronous operation is preserved.
Data Source
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AI summary
The invention relates to a locally synchronous GALS circuit comprising a circuit wrapper and a locally synchronous circuit module connected to the circuit wrapper. The circuit wrapper (350) comprises a request input (REQ_A) for request signals of an external GALS circuit, a data input for data signals (DATA_IN) of the external GALS circuit and a clock input for a periodical clock signal of an external clock generator. The circuit wrapper derives an internal request signal from the external request signal, which displays that validated data signals are received at a data input. The internal request signal is transferred to the locally synchronous circuit via an internal request interface. An internal clock signal (INT_CLK) is derived form the external clock signal and is delivered to the locally synchronous circuit module via the internal clock interface. The GALS circuit comprises a jitter generator (352) arranged in the appropriate location of the external or internal request signal or the external or internal clock signal path and is designed in such a way that a corresponding signal is received and transmitted with a random signal delay.