GALS NoC Router Clocking for Scalable Heterogeneous SoCs
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Solution Overview
Problem
Traditional network-on-chip (NoC) interconnects face scalability challenges due to rigid clocking requirements, especially in large System-on-Chips (SoCs) with heterogeneous components, where maintaining synchronized clock distribution across numerous sequential elements is impractical and power-intensive, necessitating a more flexible clocking approach.
Innovation Solution
The implementation of a Globally Asynchronous Locally Synchronous (GALS) micro-architecture for NoC routers allows for arbitrary clock domain partitions, enabling flexible clock domain crossing and synchronization through dual-clock FIFOs and credit synchronization circuits, which decouples clocking between NoC and host blocks, allowing for independent clock frequencies and reduced clock skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional synchronized clock distribution is used across NoC interconnects, then clock synchronization is maintained, but scalability and power consumption deteriorate in large SoCs with heterogeneous components
Solution Approach 1:
The patent divides the clock distribution system into multiple independent clock domains, where each domain can operate autonomously with its own clock frequency and phase. This segmentation allows different regions of the NoC to be clocked independently, enabling scalability to heterogeneous components while maintaining synchronization within each domain through boundary synchronization mechanisms.
Solution Approach 2:
The patent implements locally synchronous operation where each clock domain maintains synchronous timing locally within its boundaries, while allowing different local characteristics (frequencies, phases) across domains. This local quality approach enables heterogeneous components to operate at their optimal frequencies while still achieving global coordination through controlled synchronization at domain boundaries.
2Device complexity
If a single global clock is used across the NoC, then timing synchronization is simplified, but clock skew and power consumption increase with network size
Solution Approach 1:
The patent segments the monolithic global clock into multiple regional clocks, each serving a specific clock domain. This reduces the distribution distance and complexity for each clock signal, thereby lowering power consumption and minimizing clock skew within each domain. The segmentation maintains timing simplicity locally while enabling scalable global operation.
Solution Approach 2:
The patent transitions from a single-dimension global clock hierarchy to a multi-dimensional clock domain structure, where clock synchronization occurs both locally within domains and globally across domain boundaries. This dimensional change enables parallel clock distribution paths, reducing overall power consumption and complexity.
3Adaptability or versatility
If multiple clock domains are implemented for flexibility, then adaptability to heterogeneous components improves, but clock domain crossing complexity increases
Solution Approach 1:
The patent introduces boundary synchronization mechanisms as intermediaries between clock domains. These boundaries act as mediators that manage data transfer and synchronization between domains with different clock frequencies and phases, abstracting the complexity of clock domain crossing while enabling flexible heterogeneous component integration.
Solution Approach 2:
The patent implements preliminary synchronization setup at clock domain boundaries before data transfer occurs. By pre-establishing synchronization handshaking and timing alignment mechanisms in advance, the system reduces the complexity of real-time clock domain crossing and enables smoother integration of heterogeneous components.
Data Source
AI summary
Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.