Resonant Galvanic Isolation IC Layout for Voltage Transient Reliability
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Solution Overview
Problem
Existing galvanic isolators face challenges in providing high efficiency and reliability, particularly in managing signal transmission between circuits with different reference potentials, as they can malfunction due to high voltage changes, leading to current transmission issues that may damage circuits.
Innovation Solution
The integration of inductors and capacitors in a semiconductor process, where the inductors are inductively coupled and capacitors are strategically placed to generate resonant frequencies, ensuring effective signal transmission while maintaining isolation voltage, and the physical separation of inductors reduces parasitic resistance and current flow during voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If galvanic isolation is implemented using conventional isolators, then signal transmission between circuits with different reference potentials is enabled, but the isolators may malfunction due to high voltage changes, leading to current transmission issues
Solution Approach 1:
The isolator is divided into two separate integrated circuits (first and second isolators) that are physically separated. Each isolator handles one direction of signal transmission, and they are connected through magnetic coupling rather than direct electrical connection. This segmentation prevents high voltage changes in one circuit from directly affecting the other, thereby improving reliability during voltage transients.
Solution Approach 2:
A magnetic field serves as an intermediary between the two isolators, enabling signal transmission without direct electrical contact. The first inductor in the first isolator magnetically couples with the second inductor in the second isolator, allowing signals to pass through the magnetic field while blocking harmful voltage changes and current flows. This intermediary mechanism protects against malfunction during high voltage changes.
2Area of stationary object
If inductors are placed close together for compact design, then device area is reduced, but parasitic resistance increases and signal transmission efficiency decreases
Solution Approach 1:
The patent utilizes vertical stacking of conductive layers to achieve compact design. Inductors are formed in different conductive layers (first, second, and third conductive layers) with vertical separation, allowing close horizontal placement while maintaining adequate vertical spacing. This reduces parasitic resistance between inductors while minimizing the overall device footprint, thus reducing energy loss without sacrificing compactness.
3Area of stationary object
If capacitor electrodes are positioned close to inductors for compact layout, then device area is reduced, but insulation requirements increase and manufacturing complexity rises
Solution Approach 1:
The capacitor electrodes are positioned in different vertical layers relative to the inductors. The first capacitor has electrodes in the first and second conductive layers, while the second capacitor has electrodes in the second and third conductive layers. This vertical separation in the layer structure allows compact horizontal layout while maintaining adequate insulation distance through the dielectric layers, reducing manufacturing complexity compared to horizontal separation approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances signal transmission efficiency, reduces the risk of circuit malfunction, and provides reliable galvanic isolation by controlling current flow during voltage changes, thereby improving the overall performance and reliability of the galvanic isolator.
Implementation Method 1
a second inductor disposed in a second conductive layer above the first conductive layer and inductively coupled to the first inductor
Implementation Method 2
a first capacitor including a first electrode disposed in the first conductive layer and electrically connected to the first inductor and a second electrode disposed in the second conductive layer and electrically connected to a first bonding wire
Data Source
AI summary
A device includes a first integrated circuit, where the first integrated circuit includes a first inductor comprising a first pattern disposed in a first conductive layer. The first integrated circuit further comprises a first capacitor including a first electrode disposed in the first conductive layer and electrically connected to the first inductor and a second electrode disposed in a second conductive layer above the first conductive layer and electrically connected to a first bonding wire.