Galvanic Isolation via Inductive Coupling in Semiconductor Packages
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Solution Overview
Problem
There is a need for semiconductor device packaging that provides galvanic isolation between IC dies operating at different supply voltages to prevent electrical over stress damage from affecting other dies.
Innovation Solution
The packaging includes a first semiconductor die and a second semiconductor die attached to a package substrate, with inductive coils on one die and in the substrate allowing for communication while maintaining electrical isolation, ensuring that if one die is damaged, the other remains isolated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct electrical connection is used between IC dies, then communication and power transfer are simple and efficient, but electrical over stress can damage other dies operating at different voltages
Solution Approach 1:
The patent introduces an intermediary isolation structure comprising a first isolation layer and a second isolation layer positioned between the first IC die and the second IC die. This intermediary structure provides galvanic isolation, preventing direct electrical connection while allowing controlled signal and power transfer, thus protecting against electrical over stress without completely isolating the functional interfaces.
Solution Approach 2:
The isolation structure is segmented into multiple distinct layers: a first isolation layer and a second isolation layer, each serving specific isolation functions. This segmentation allows the patent to provide comprehensive galvanic isolation while maintaining functional interfaces, resolving the contradiction between protection and complexity through structured layering.
2Reliability
If isolation structure is added between IC dies, then protection from electrical over stress is improved, but manufacturing complexity increases
Solution Approach 1:
The isolation layers are integrated into the packaging substrate during the manufacturing process, with the first isolation layer and second isolation layer being formed as part of the substrate structure before the IC dies are mounted. This preliminary integration reduces the number of separate manufacturing steps required, easing the manufacturing process while maintaining the protection benefits.
3Reliability
If galvanic isolation is implemented, then electrical safety between different voltage dies is ensured, but direct current electrical conductive path is blocked
Solution Approach 1:
The isolation structure serves as an intermediary that blocks direct current electrical conductive paths while allowing controlled power and signal transfer through the isolation layers. The first isolation layer and second isolation layer are designed to provide galvanic isolation for DC paths while maintaining functionality for AC signals and controlled power transfer, thus resolving the contradiction between electrical safety and power transfer capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively isolates high and low voltage dies, preventing damage from electrical over stress and enabling safe communication and power transfer between them.
Implementation Method 1
The two semiconductor die are configured to communicate and/or transfer power with one another by way of inductive coils—at least a first coil located on one of the semiconductor die and a second coil located in the package substrate
Data Source
AI summary
A semiconductor device package having galvanic isolation is provided. The semiconductor device package includes a package substrate having a first inductive coil. A first semiconductor die is attached to a first major surface of the package substrate. The first semiconductor die includes a second inductive coil substantially aligned with the first inductive coil. A second semiconductor die is attached to the first major surface of the package substrate. A wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.