GaN 3D IC Integration for Compact High-Frequency Power And RF
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Solution Overview
Problem
Current semiconductor technologies, such as Si and III-V, face limitations in power delivery and RF communication due to fundamental constraints, necessitating the development of more advanced technologies to achieve better energy efficiency, performance, and smaller form factors.
Innovation Solution
The integration of gallium nitride (GaN) three-dimensional integrated circuit technology, which includes monolithic 3D integration of GaN NMOS and Si CMOS, enables the creation of compact, efficient power delivery and RF solutions by leveraging GaN's wide bandgap properties and the integration of dissimilar semiconductor technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If Si and III-V technologies are used for power delivery and RF communication, then basic functionality is achieved, but energy efficiency and performance are limited due to fundamental constraints
Solution Approach 1:
The patent employs a hybrid integrated circuit architecture that combines GaN HEMT devices on a first substrate with Si CMOS circuitry on a second substrate. This composite structure leverages the high electron mobility and wide bandgap properties of GaN for power delivery and RF functions, while utilizing the mature, cost-effective Si CMOS for digital processing and control, thereby achieving superior energy efficiency without sacrificing performance reliability
Solution Approach 2:
The patent divides the integrated circuit into distinct functional segments: a GaN-based power delivery and RF section on a first substrate, and a Si-based digital processing section on a second substrate. This segmentation allows each technology to operate in its optimal performance regime, with the GaN section handling high-power, high-frequency operations and the Si section handling low-power digital logic, thus resolving the fundamental constraints of using单一 technology
2Power
If advanced semiconductor technology is developed to improve energy efficiency and performance, then better power delivery and RF output are achieved, but form factor constraints increase
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by placing the GaN power delivery substrate and Si digital processing substrate in vertical layers. This vertical integration approach, enabled by through-silicon via (TSV) technology, allows high-power functionality to be achieved in a compact footprint by utilizing the third dimension (height/depth), thereby resolving the conflict between power delivery capability and form factor
Solution Approach 2:
The patent implements a nested structure where the Si CMOS substrate is positioned beneath the GaN HEMT substrate, with interconnect structures penetrating through the Si substrate to establish electrical connections. This nested arrangement allows the digital processing functions to be embedded within the overall device structure, maximizing space utilization and achieving high power delivery in a compact form factor
3Productivity
If multiple functionalities are integrated onto a single die, then device density and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the multiple functionalities into distinct technology nodes: GaN HEMT devices for power delivery and RF, and Si CMOS for digital processing. Each segment is fabricated using optimized process flows for its specific technology, then integrated through standardized interconnect structures (TSVs and bonding interfaces). This segmentation approach achieves high device density while managing manufacturing complexity by avoiding the need to integrate dissimilar technologies at a single fabrication node
Solution Approach 2:
The patent introduces intermediate structures to facilitate integration between the GaN and Si substrates, including TSVs that penetrate the Si substrate, bonding pads for wafer-level or chip-level bonding, and interconnect layers that bridge the two technologies. These intermediary elements serve as standardized interfaces that simplify the integration process, allowing multiple functionalities to be combined without proportionally increasing manufacturing complexity
Data Source
AI summary
Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.