GaN Digital Power Amplifier Driver for High-Frequency Efficiency
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Solution Overview
Problem
Digital power amplifiers in wireless communication systems face efficiency and size challenges due to high parasitic capacitances and limited switching speed, particularly at higher frequencies, which are exacerbated by high source impedance in the driver stage.
Innovation Solution
A digital power amplifier design featuring a low output impedance driver stage with a pre-driver and driver circuit configuration, utilizing differential amplifiers and current mode class-D push-pull output stages with gallium nitride transistors to reduce source impedance and enhance switching speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high power transistors are used to increase power output, then power output is improved, but parasitic capacitances increase which reduces efficiency at higher frequencies
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional semiconductor to gallium nitride (GaN), which fundamentally alters the parasitic capacitance characteristics. GaN transistors exhibit lower parasitic capacitances compared to conventional transistors of the same power rating, allowing high power output to be maintained while reducing the efficiency loss caused by parasitic capacitances at higher frequencies.
2Device complexity
If conventional driver stage with high source impedance is used, then circuit simplicity is maintained, but switching speed is limited which reduces efficiency at higher frequencies
Solution Approach 1:
The driver stage is segmented into multiple cascaded stages (first driver stage, second driver stage, third driver stage) rather than using a single conventional driver. This segmentation allows each stage to contribute to progressively lowering the output impedance, enabling the final driver stage to provide the low source impedance needed for high switching speed while distributing the complexity across multiple manageable stages.
Solution Approach 2:
The patent systematically changes the output impedance parameter across the driver stages, with each subsequent stage having lower output impedance than the previous stage. The final driver stage is designed with specifically low output impedance to match and drive the GaN power transistor efficiently, enabling fast switching speeds required for high frequency operation.
3Speed
If transistor size is increased to reduce charging/discharging time constant, then switching speed is improved, but parasitic capacitances increase which reduces efficiency
Solution Approach 1:
The patent changes the material parameter to gallium nitride, which fundamentally alters the relationship between transistor size and parasitic capacitance. In GaN transistors, the parasitic capacitances do not increase proportionally with device size as they do in conventional transistors, allowing larger transistors to be used for high power applications without the same penalty in parasitic capacitance, thus enabling fast switching with maintained efficiency.
Data Source
AI summary
A digital power amplifier (or power switching amplifier or power switch) for use in a digital transmitter includes a low impedance multi-stage driver circuit having a low impedance pre-driver and a low impedance driver. The drive circuit drives a power switch stage having two power transistors configured in a current mode class-D push-pull configuration. Utilization of gallium nitride (GaN) transistors or pseudomorphic high electronic mobility transistors (pHEMT) (or combination thereof) and sizing the transistors progressively larger in the driver than in the pre-driver (at least about 3×) provides a reduction in output impedance of the driver circuit and progressive increases in the power driving capability of the succeeding stage. This allows the use of a power amplifier at higher frequencies without altering or affecting the power efficiency and allows use of a digital power amplifier for a digital transmitter.