GaN RF Transistor Amplifier Vias for Bond Wire Inductance Limits

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Solution Overview

Problem

Conventional RF transistor amplifiers face challenges in high-frequency applications due to excessive inductance from bond wires, leading to performance degradation and increased manufacturing costs, as well as size limitations and variability in inductance values affecting impedance matching and harmonic termination.

Innovation Solution

The RF transistor amplifiers feature conductive gate and drain vias that connect the transistor terminals to an interconnection structure, reducing inductance and allowing for flexible matching network configurations, eliminating the need for bond wires and enabling smaller die sizes and improved manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bond wires are used to connect transistor terminals to interconnection structure, then electrical connections can be established, but inductance increases and performance degrades at high frequencies

Engineering Contradiction:
ImproveperformanceVSAvoidinductance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes bond wires from the interconnection structure, extracting the harmful inductive element while maintaining electrical connectivity through alternative via-based connections. This eliminates the source of excessive inductance that degrades high-frequency performance.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical bond wire connection system with an integrated conductive via system embedded in the interconnection structure. This substitution eliminates the parasitic inductance inherent in wire-based connections while providing more controlled and predictable electrical pathways.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of manufacture

If bond wires are used for connections, then manufacturing can proceed with conventional processes, but manufacturing costs increase and process variations affect inductance values

Engineering Contradiction:
Improvemanufacturing processVSAvoidmanufacturing efficiency
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent merges the connection structure into the interconnection substrate itself, integrating conductive vias directly into the manufacturing process. This consolidation eliminates separate bond wire attachment steps, reducing manufacturing complexity and improving efficiency while ensuring consistent electrical characteristics.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of operation

If conventional bond wire connections are used, then connections can be made, but die size must be larger to accommodate bond wire routing

Engineering Contradiction:
Improveconnection capabilityVSAvoiddie size
Core Design Contradiction:
Ease of operationVSArea of moving object

Solution Approach 1:

The patent transitions from surface-level bond wire connections to vertically-integrated conductive vias embedded within the interconnection structure. This dimensional change allows connections to be made through the substrate thickness rather than across the surface, significantly reducing the required die area while maintaining connection capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11863130B2Group III nitride-based radio frequency transistor amplifiers having source, gate and/or drain conductive vias
Publication Date: 2024.01.02 MACOM TECH SOLUTIONS HLDG INC
  • US11863130B2 patent drawing
  • US11863130B2 patent drawing
  • US11863130B2 patent drawing

AI summary

RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.