GaN Power Device Backside Bonding via Patterned Backmetals
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Solution Overview
Problem
Gallium nitride (GaN) power devices face challenges in packaging due to the need for numerous small-diameter bond wires, which increase packaging cost and inductance, affecting switching characteristics, and existing flip-chip processes result in poor thermal contact and high thermal resistance.
Innovation Solution
A power device packaging structure featuring a semi-insulating substrate with epitaxial layers and patterned backmetals through vias, a power module substrate with isolation regions, thermal shunts for heat management, and additional circuit elements for current and overvoltage protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If small-diameter bond wires are used to connect minimized source and drain pads, then die area is minimized, but packaging cost increases and inductance increases affecting switching characteristics
Solution Approach 1:
The patent moves the bond pads from the front surface to the back surface of the die, utilizing the backside area for electrical connections. This dimensional relocation allows large-diameter wires to be used without increasing the front die area, as the bonds are made on the opposite surface of the device.
Solution Approach 2:
The device is divided into functionally separate regions: the front surface contains the active transistor structure, while the back surface contains the electrical connection pads. This segmentation allows independent optimization of each surface for its specific function, enabling large wire bonds on the back without affecting the compact front die area.
2Device complexity
If large diameter bond wires, ribbons, or clips are used to reduce inductance and packaging cost, then switching characteristics improve, but die area significantly increases
Solution Approach 1:
By relocating the bond pads to the back surface of the die, the patent creates available space on the front surface while providing adequate area on the back surface for large-diameter wire connections. This resolves the conflict between using large wires for low inductance and maintaining compact die area.
3Device complexity
If flip-chip process is used to attach die to substrate, then assembly complexity is reduced, but thermal contact becomes poor resulting in high thermal resistance
Solution Approach 1:
Instead of attaching the front surface of the die to the substrate (conventional flip-chip), the patent inverts the approach by attaching the back surface to the substrate. This allows the front surface with its active structures to maintain optimal orientation while achieving both simplified assembly and improved thermal contact through the substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces packaging cost and complexity while maintaining low inductance and improving thermal performance, enabling efficient heat dissipation and protection against surges.
Implementation Method 1
Bond pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside
Implementation Method 2
The thermal shunt conducts heat away from the semi-insulating substrate, and in turn away from the epitaxial layers
Data Source
AI summary
The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.


