GaN Barrier Thickness Optimization for Dislocation Control

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Solution Overview

Problem

Semiconductor light emitting elements with GaN layers grown on foreign substrates suffer from high dislocation and crystal defects, leading to reduced light emitting efficiency and increased serial resistance, hindering the achievement of high luminosity and efficiency.

Innovation Solution

The semiconductor light emitting element features barrier layers with a thickness 1.5 times or more greater than adjacent well layers, made of undoped GaN, AlGaN, or InGaN with a lower In mixed crystal ratio, and includes cap layers with different compositions between well and barrier layers, alternately stacked to reduce defects and serial resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If a GaN layer is grown on a foreign substrate, then a flat substrate surface can be obtained, but numerous dislocations are transferred through the semiconductor layers

Engineering Contradiction:
Improvesubstrate surface flatnessVSAvoiddislocation density
Core Design Contradiction:
ShapeVSReliability

Solution Approach 1:

The patent uses an undoped GaN layer as an intermediate buffer layer between the foreign substrate and the doped semiconductor layers. This intermediary layer absorbs and isolates dislocations from the active region, preventing them from propagating through the functional layers while still providing a flat surface for subsequent layer growth.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the thickness of well layers in the active layer is increased, then light emitting efficiency may improve, but dislocation and defect occurrence increases

Engineering Contradiction:
Improvelight emitting efficiencyVSAvoiddefect density
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent optimizes the thickness parameter of well layers to be 3 nm or less, and sets the barrier layer thickness to 1.5 times or more of the well layer thickness. By changing these dimensional parameters and creating an asymmetric thickness ratio, the patent achieves high light emitting efficiency while minimizing dislocation propagation and defect formation.

Inventive Principle:
Principle #35Parameter changes

3Illumination intensity

If the number of stacking layers in the active layer is increased, then light output may increase, but serial resistance increases

Engineering Contradiction:
Improvelight outputVSAvoidserial resistance
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent applies different doping conditions to different regions: the undoped GaN layer is positioned in the active region where high-quality crystal growth is critical, while doped layers are placed in the cladding regions where electrical conductivity is prioritized. This local differentiation allows multiple stacking layers to increase light output without proportionally increasing serial resistance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP2738824B1Semiconductor light-emitting element
Publication Date: 2022.08.24 NICHIA CORP
  • EP2738824B1 patent drawingFigure 1
  • EP2738824B1 patent drawingFigure 2
  • EP2738824B1 patent drawingFigure 3~4

AI summary

A semiconductor light emitting element includes an n-side semiconductor layer, an active layer, and a p-side semiconductor layer stacked in this order on a substrate, the active layer includes a multiple quantum well structure which includes a plurality of barrier layers and a plurality of well layers adjacent to the barrier layers, and of the barrier layers, a final barrier layer disposed at a side closest to the p-side semiconductor layer and one or more barrier layers adjacent to the final barrier layer via the well layers respectively has a greater thickness than a thickness of a barrier layer at a side close to the n-side semiconductor layer.