Hybrid GaN-BCD Heteroepitaxy on Silicon for Deep Trench Isolation
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Solution Overview
Problem
Existing semiconductor devices struggle to integrate heterogeneous semiconductor layers, such as gallium nitride (GaN) layers, aluminum nitride (AlN) layers, and aluminum gallium nitride (AlGaN) layers, on a silicon wafer effectively, which affects the performance and integration of bipolar junction transistors (BJTs), complementary metal oxide semiconductor (CMOS) transistors, and double diffused metal oxide semiconductor (DMOS) transistors (BCD) devices.
Innovation Solution
A semiconductor device is fabricated with a silicon (100) lattice structure substrate, incorporating a gallium nitride (GaN) area adjacent to a bipolar junction transistor (BJT) complementary metal oxide semiconductor (CMOS) double diffused metal oxide semiconductor (DMOS) (BCD) area, utilizing deep trench structures for isolation and epitaxial layers with specific doping and metallization layers for conductive paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If heterogeneous semiconductor layers (GaN, AlN, AlGaN) are integrated on a silicon wafer, then device performance and functionality are improved, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into distinct functional areas: a first area containing GaN-based high voltage devices and a second area containing BCD devices. This segmentation allows each area to be optimized independently for its specific function while being fabricated on a common silicon substrate, thereby managing integration complexity while achieving high performance.
Solution Approach 2:
The patent applies local quality by creating region-specific device structures and processing conditions. The GaN area receives specialized epitaxial growth and device fabrication steps tailored for wide-bandgap materials, while the BCD area undergoes conventional silicon processing. This localized approach enables optimal performance in each region without compromising the entire device structure.
2Adaptability or versatility
If multiple transistor types (BJT, CMOS, DMOS) are combined on a single BCD device, then functionality and application range are improved, but device complexity increases
Solution Approach 1:
The patent merges three different transistor technologies (BJT, CMOS, and DMOS) into a single integrated BCD device structure. This consolidation allows multiple functions to be achieved in one device package, reducing system-level complexity and improving application versatility while maintaining manufacturability through unified processing steps.
Solution Approach 2:
The BCD device structure is designed with universal characteristics that accommodate multiple transistor types. The device architecture incorporates regions and layers that can be configured to form BJT, CMOS, or DMOS transistors, allowing a single device structure to perform multiple functions and serve diverse application requirements.
3Reliability
If deep trench structures are used for isolation, then device reliability is improved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent implements deep trench isolation structures early in the fabrication process, before subsequent device formation steps. By preparing the isolation structures in advance, the patent simplifies later processing steps and ensures proper electrical isolation is established before devices are constructed, thereby improving reliability without significantly increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integration of GaN and BCD areas on a single substrate enhances device performance, reducing power loss, system size, and cost while improving efficiency and enabling high voltage operations up to 120V.
Implementation Method 1
forming a gallium nitride (GaN) area on the first substrate... forming a bipolar junction transistor (BJT) complementary metal oxide semiconductor (CMOS) double diffused metal oxide semiconductor (DMOS) (BCD) area adjacent to the GaN area
Data Source
AI summary
According to one aspect of the present disclosure, a semiconductor device includes a first substrate having a lattice structure, wherein the first substrate includes a gallium nitride (GaN) area adjacent to a bipolar junction transistor (BJT) complementary metal oxide semiconductor (CMOS) double diffused metal oxide semiconductor (DMOS) (BCD) area. In some embodiments, the GaN area comprises one or more GaN device layers disposed on the first substrate. In some embodiments, the BCD area comprises one or more BCD device layers. In some embodiments, the first substrate comprises a silicon (100) lattice structure configuration. In some embodiments, the GaN devices layers comprise one or more GaN device layers having a cubic structure and one or more GaN device layers having a wurtzite structure.