GaN Bipolar Charge-Trapping Memory Single Insulating Layer
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Solution Overview
Problem
Traditional charge-trapping non-volatile memory devices face challenges in achieving high programming/erasing speed, endurance, and long retention time, with existing solutions compromising on one or more of these factors due to the limitations of silicon's narrow bandgap.
Innovation Solution
A wide-bandgap semiconductor bipolar charge-trapping non-volatile memory structure with a single insulating layer, utilizing materials like gallium nitride (GaN) to enhance data retention and speed, allowing for sub-nanosecond programming/erasing speed and over 10^8 cycles with retention times exceeding 10 years.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a thin tunnel oxide layer is used to enable fast programming/erasing speed, then P/E speed is improved, but electrical stress on the tunnel oxide layer increases and endurance deteriorates
Solution Approach 1:
The patent changes the fundamental material parameter from silicon-based tunnel oxide to wide-bandgap semiconductor material (GaN, SiC, or diamond), which fundamentally alters the electrical stress characteristics and enables both fast P/E speed and high endurance simultaneously
Solution Approach 2:
The patent employs composite material structures where wide-bandgap semiconductor materials form the tunnel oxide equivalent layer, combined with charge trapping layers and blocking oxide layers to achieve superior performance in both speed and endurance
2Speed
If high P/E voltage is applied to achieve fast programming/erasing speed, then P/E speed is improved, but electrical stress on the tunnel oxide layer increases and endurance deteriorates
Solution Approach 1:
The patent changes the bandgap parameter from narrow (silicon) to wide (GaN, SiC, diamond), which fundamentally changes the voltage-stress relationship and allows high-speed operation without excessive electrical stress accumulation
Solution Approach 2:
The patent uses wide-bandgap semiconductor materials that can withstand high electrical stress without degradation, effectively making the tunnel oxide layer resistant to damage from high-voltage P/E operations
3Reliability
If a thick tunnel oxide layer is used to reduce electrical stress and improve endurance, then endurance is improved, but programming/erasing speed deteriorates
Solution Approach 1:
The patent changes the material composition parameter to wide-bandgap semiconductors, which enable thin layer usage with both low electrical stress and high charge transfer efficiency, resolving the thickness-speed-endurance tradeoff
4Duration of action of stationary object
If traditional silicon-based charge-trapping memory is used to achieve long retention time, then retention time is improved, but programming/erasing speed and endurance deteriorate
Solution Approach 1:
The patent changes the bandgap parameter from narrow (1.1 eV for silicon) to wide (3.4 eV for GaN, 3.26 eV for SiC), which simultaneously improves retention time, P/E speed, and endurance by enabling better charge confinement and reduced tunneling leakage
Solution Approach 2:
The patent uses composite material stacks with wide-bandgap semiconductors forming the channel and tunnel oxide equivalent, combined with carefully engineered charge trapping and blocking layers to achieve superior overall performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure achieves high programming/erasing speed, enhanced endurance, and extended retention time, integrating well with existing electronics and optoelectronics, while reducing electrical stress on the memory layer.
Implementation Method 1
wide-bandgap (WBG) semiconductor bipolar charge trapping (BCT) non-volatile memory
Implementation Method 2
an appreciable carrier transport occurs with a reduced E-field in the proposed structure since the external bias compensates the built-in potential
Data Source
AI summary
Provided herein are a wide-bandgap semiconductor bipolar charge trapping (BCT) non-volatile memory structure with only one single insulating layer and a fabrication method thereof. Monolithically integrated enhancement-mode (E-mode) n-channel and p-channel field effect transistors (n-FETs and p-FETs) for gallium nitride (GaN)-based complementary logic (CL) gates based on the proposed memory structure, together with a fabrication method thereof in a single process run and various logic circuits incorporating one or more of the GaN-based CL gates, are also provided herein.